Enum CondNode 

pub enum CondNode {
    Signal(TerminalRef),
    Specparam(SymbolId),
    Const(Vec<Bit4>),
    Unary(CondUnaryOp, Box<CondNode>),
    Binary(CondBinaryOp, Box<CondNode>, Box<CondNode>),
    Ternary(Box<CondNode>, Box<CondNode>, Box<CondNode>),
    Concat(Vec<CondNode>),
    Replication(u32, Box<CondNode>),
}

A state-dependent path’s own if (cond) conditional expression (LRM 30.4.4.1, Task 8), resolved to data that needs no further sv_lang/live Design access to evaluate – the same “discover the SHAPE now, evaluate the VALUE later, against live simulation state” split PathEntry::delays’s own doc comment already establishes, except a condition’s VALUE is never baked even once at plan time (unlike a delay): LRM 30.4.4.1’s own operand list (“module input/inout ports… locally defined variables or nets… compile-time constants”) means a condition’s truth genuinely depends on LIVE simulation state, re-read on every check (sv-sim-bin::specify’s own CondEval, this type’s plan-time-Loc/register-time-Place-resolved sibling, is the runtime evaluator – this crate carries only the symbolic shape).

Variants

Signal(TerminalRef)

A signal terminal (whole signal, or a constant bit-select/ part-select of one) – LRM 30.4.4.1’s own “ports… variables or nets… or their bit-/part-selects”.

Specparam(SymbolId)

A Specparam symbol – LRM 30.4.4.1’s own “compile-time constants (constant numbers and specify parameters)”. Resolved against TimingModel::specparam at sv-sim-bin::specify::plan time (not evaluated here, and not carried as a live value past that point – see that crate’s own compile_cond_plan doc comment for why a condition’s specparam operand is, as of this task, baked once at plan time rather than re-read on every check the way a Signal leaf is).

Const(Vec<Bit4>)

A plain compile-time-constant value (LRM 30.4.4.1’s own “constant numbers”), already evaluated at discovery time – LSB-first, in sv_lang::SVInt::bits’s own bit order.

Unary(CondUnaryOp, Box<CondNode>)

Binary(CondBinaryOp, Box<CondNode>, Box<CondNode>)

Ternary(Box<CondNode>, Box<CondNode>, Box<CondNode>)

c ? t : f – the plain (non-pattern-matching) ternary form only; a &&&-chained pattern-matching conditional is rejected at [compile_cond_expr] (Table 30-1 does not list it).

Concat(Vec<CondNode>)

{a, b, ...}, in SOURCE order (first element MSB-most, matching Expression::operands()’s own documented order) – never reordered here; sv-sim-bin::specify’s own runtime evaluator is where MSB-first source order meets this crate’s own LSB-first per-bit storage convention.

Replication(u32, Box<CondNode>)

{n{x}} – n, the replication count, already evaluated to a compile-time constant at discovery time (LRM 11.4.12.1’s own requirement, verified live: slang already enforces this upstream).

Trait Implementations

impl Clone for CondNode

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CondNode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for CondNode

impl PartialEq for CondNode

fn eq(&self, other: &Self) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for CondNode