Struct PathEntry 

pub struct PathEntry {

    pub instance: InstanceId,
    pub inputs: Vec<TerminalRef>,
    pub outputs: Vec<TerminalRef>,
    pub connection: TimingPathConnectionKind,
    pub polarity: TimingPathPolarity,
    pub path_uid: SymbolId,
    pub delays: PathDelaySet,
    pub edge: PathEdge,
    pub edge_data_source_name: Option<String>,
    pub condition: PathCondition,
    pub reject_limit: PathDelaySet,
    pub error_limit: PathDelaySet,
    pub pulse_style: PulseStyle,
    pub showcancelled: bool,
}

A TimingPath (LRM §30.4), post multi-path desugaring (30.4.6): one PathEntry per individual module path assignment, after a multi-input/ multi-output full-connection declaration ((a, b, c *> q1, q2) = 10;) has been expanded into its six (here: inputs.len() * outputs.len()) one-to-one assignments per 30.4.6’s own worked example. inputs/ outputs therefore always have exactly one element each as of this task (Task 3) — kept as Vec (matching the plan’s own §1.1 pseudocode) because a later task’s vector-terminal handling reads them the same way regardless of how many elements they end up holding.

Bare shell beyond this — Track A (Task 4a onward) fills in the rest of §1.1’s own field list (polarity/edge/condition/delays/ reject_limit/error_limit/pulse_style/showcancelled).

Fields

instance: InstanceId

The instance the path’s declaration lives in.

inputs: Vec<TerminalRef>

This path’s one resolved source terminal (LRM 30.4.1: always a net).

outputs: Vec<TerminalRef>

This path’s one resolved destination terminal (LRM 30.4.1: a net or a variable).

connection: TimingPathConnectionKind

*> (Full) or => (Parallel) — metadata only at this task; T4a is where it starts to matter (full connection’s fan-in/fan-out vs. parallel’s bit-paired semantics).

polarity: TimingPathPolarity

This path’s own overall polarity (LRM §30.4.7: the +/- on the path operator itself, e.g. the + of (a +*> b) = 1; — path. timing_path_polarity(), NOT timing_path_edge_polarity(), which is an edge-sensitive path’s own, separate destination-suffix polarity and T7’s scope, not this one). Per §30.4.7.1/.2/.3’s own text — “does not affect the actual propagation of data” — this is metadata ONLY: stored here so a debug/VPI-facing accessor (PathEntry::polarity) can read it back, and never consulted by any delay/timing computation. sv-sim-bin::specify::PathRetimer — the only runtime reader of a PathEntry’s timing data — never reads this field (its own fields are src/delays/prev/shared/kick, and plan never copies polarity into RetimerPlan); see that crate’s own path_retimer_never_reads_polarity_in_its_delay_computation test for the behavioral proof.

path_uid: SymbolId

The ORIGINAL (pre-desugaring) TimingPath symbol’s own identity (LRM 30.4.6): several desugared PathEntrys share one path_uid when they came from one multi-terminal declaration, since they also share its one delay list. sv-sim-bin’s own plan-time delay evaluation (Task 4a) uses it to re-locate that original symbol – see PathEntry::delays’s own doc comment for why evaluation cannot happen inside this crate.

delays: PathDelaySet

This path’s own 12-entry transition-delay table (LRM Table 30-2/ 30-3), in scheduler ticks. PathDelaySet::default() (all zero) until sv-sim-bin’s own plan-time pass attaches the real, timescale-converted value via TimingModel::set_path_delays – evaluating a path_delay_value expression needs both sv_lang::EvalSession (constant-folding) and sv-sim-codegen:: timescale (unit/precision conversion); this crate’s own frontend feature carries the former but can never depend on the latter (sv-sim-codegen depends on sv-sim-sim, never the reverse), so the two-step “discover the SHAPE, then attach the VALUE” split this field forces mirrors TimingModel::set_specparam’s own, already-established precedent exactly. Never read before that attach call runs (crate::specify::discover’s own call order, sv-sim-bin’s run.rs wiring) – the module-path retimer process is the only runtime reader, and it is planned strictly after this field is set.

edge: PathEdge

This path’s own edge-sensitivity (LRM 30.4.3, Task 7) — see PathEdge’s own doc comment. [sv-sim-bin::specify::PathRetimer] is the only runtime reader, and reads it to GATE which of this destination’s candidate module paths are “active” for a given transition (LRM 30.4.3’s own text: “which only occur when a specified edge occurs at the source signal”), never to decide the destination’s VALUE (still never this module’s job — decision 3, unchanged by this task).

edge_data_source_name: Option<String>

The edge-sensitive suffix’s own data-source expression (LRM 30.4.3: “the d of (posedge clk => (q +: d))”), reduced to its referenced symbol’s own name for debug/VPI purposes — None both for a non-edge-sensitive path and for an edge-sensitive one whose data source is not a plain named reference (an arbitrary expression per the LRM’s own text; losing fidelity for a complex expression is harmless, since this field is documented, by both the LRM (“does not affect the actual propagation of data or events”) and this crate’s own Self::debug_edge_source_expr_name accessor, as read ONCE here (via PathEdge::from_accessors, Self::edge’s own sibling value from the SAME call) and never again — see sv-sim-bin::specify’s own edge_source_expr_text_never_affects_scheduled_timing test for the behavioral proof.

condition: PathCondition

This path’s own state-dependency (LRM 30.4.4, Task 8) – see PathCondition’s own doc comment. sv-sim-bin::specify:: PathRetimer::select_delay reads it (through sv-sim-bin’s own plan-time CondPlan/register-time CondEval compilation of the CondNode it carries) to gate this entry’s own eligibility alongside Self::edge’s existing edge gate – both decision 3’s “only when a specify path is actually active for it.”

reject_limit: PathDelaySet

This path’s own per-transition REJECT limit (LRM 30.7, Task 10), in scheduler ticks: an output pulse narrower than the limit of the delay that forms its TRAILING edge is cancelled outright. Defaults (LRM 30.7: “if no limits are specified, they default to the path delay”) to Self::delays itself – every transition’s own delay – which is exactly full inertial delay; TimingModel::set_path_delays re-establishes that default every time a path’s delays are (re)set, and TimingModel::set_path_pulse_limits (a PATHPULSE$) overrides it afterwards.

error_limit: PathDelaySet

This path’s own per-transition ERROR limit (LRM 30.7, Task 10): an output pulse at least as wide as the reject limit but narrower than this one is filtered to x; one at least this wide passes. Same default and override rules as Self::reject_limit. Never smaller than it (see TimingModel::set_path_pulse_limits).

pulse_style: PulseStyle

This path’s own output’s pulse style (LRM 30.7.4.1, Task 11): whether the x that marks a filtered pulse (or, with Self::showcancelled, a negative pulse) starts at the leading edge’s scheduled time or at the moment the pulse is detected. PulseStyle::OnEvent unless a pulsestyle_ondetect declaration names an output window overlapping this path’s own (TimingModel::discover applies the declarations).

showcancelled: bool

Whether this path’s own output shows a negative pulse (LRM 30.7.4.2, Task 11) as x rather than cancelling it: false (noshowcancelled, the LRM’s own default) unless a showcancelled declaration names an overlapping output window. Same application rule as Self::pulse_style; the two settings are independent.

Implementations

impl PathEntry

pub fn debug_polarity(&self) -> TimingPathPolarity

This path’s own overall polarity (see Self::polarity’s own field doc) — the debug/VPI-facing accessor the plan’s own Task 4a acceptance text asks for. Metadata only: never called by sv-sim-bin::specify::PathRetimer’s delay computation, only by a debugger/VPI host wanting to report a path’s declared polarity back to the user.

pub fn debug_edge_source_expr_name(&self) -> Option<&str>

This path’s own edge-sensitive data-source expression, reduced to a debug name (see Self::edge_data_source_name’s own field doc) — the Task 7 sibling of Self::debug_polarity: metadata only, never called by sv-sim-bin::specify::PathRetimer’s delay computation.

Trait Implementations

impl Clone for PathEntry

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PathEntry

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for PathEntry

impl PartialEq for PathEntry

fn eq(&self, other: &Self) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for PathEntry