Trait rust_hdl::core::logic::Logic

pub trait Logic {
    fn update(&mut self);

    fn connect(&mut self) { ... }
    fn hdl(&self) -> Verilog { ... }
}

Required methods

fn update(&mut self)

Provided methods

fn connect(&mut self)

fn hdl(&self) -> Verilog

Implementations on Foreign Types

impl<L: Logic, const P: usize> Logic for [L; P]

fn update(&mut self)

Implementors

impl Logic for ICEPLL40Core

impl Logic for ClockBuffer

impl Logic for OpalKellyDownload32FIFO

impl Logic for OpalKellyDownloadFIFO

impl Logic for OpalKellyHostInterface

impl Logic for OpalKellyHost

impl Logic for BTPipeIn

impl Logic for BTPipeOut

impl Logic for PipeIn

impl Logic for PipeOut

impl Logic for TriggerIn

impl Logic for TriggerOut

impl Logic for WireIn

impl Logic for WireOut

impl Logic for OKSPIMaster

impl Logic for DDRFIFO

impl Logic for MCBInterface1GDDR2

impl Logic for CommandPort

impl Logic for MemoryInterfaceGenerator

impl Logic for ReadPort

impl Logic for WritePort

impl Logic for OpalKellyDDRBackedDownloadFIFO

impl Logic for PLLFreqSynthesis

impl Logic for OKTest1

impl Logic for OpalKellyDDRBackedDownloadFIFO7Series

impl Logic for MCBInterface4GDDR3

impl Logic for MemoryInterfaceGenerator7Series

impl Logic for OpalKellySystemClock7

impl Logic for AD7193Simulator

impl Logic for ADS868XSimulator

impl Logic for MAX31856Simulator

impl Logic for MuxedAD7193Simulators

impl Logic for MuxedMAX31856Simulators

impl Logic for EdgeDetector

impl Logic for Pulser

impl Logic for SPIWires

impl Logic for BitSynchronizer

impl<D: Direction, T: Synth> Logic for Signal<D, T>

impl<D: Synth> Logic for TristateBuffer<D>

impl<D: Synth, const N: usize> Logic for RAM<D, N>

impl<D: Synth, const N: usize> Logic for RAMWrite<D, N>

impl<D: Synth, const N: usize> Logic for ROM<D, N>

impl<D: Synth, const N: usize> Logic for SyncROM<D, N>

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOReadLogic<D, N, NP1, BLOCK_SIZE>

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for SynchronousFIFO<D, N, NP1, BLOCK_SIZE>

impl<T: Synth> Logic for BidiBusD<T>

impl<T: Synth> Logic for BidiBusM<T>

impl<T: Synth> Logic for FifoBus<T>

impl<T: Synth> Logic for DFF<T>

impl<T: Synth> Logic for SyncReceiver<T>

impl<T: Synth> Logic for SyncSender<T>

impl<T: Synth> Logic for VectorSynchronizer<T>

impl<T: Synth> Logic for Constant<T>

impl<T: Synth, const N: usize, const NP1: usize> Logic for BidiDevice<T, N, NP1>

impl<T: Synth, const N: usize, const NP1: usize> Logic for BidiMaster<T, N, NP1>

impl<U: Block> Logic for TopWrap<U>

impl<const ADDR_BITS: usize> Logic for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const DN: usize, const DW: usize> Logic for FIFOExpanderN<DN, DW>

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Logic for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

impl<const DW: usize, const DN: usize> Logic for FIFOReducerN<DW, DN>

impl<const DW: usize, const DN: usize, const REVERSE: bool> Logic for FIFOReducer<DW, DN, REVERSE>

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Logic for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

impl<const FIN_FREQ: u64, const FOUT_FREQ: u64> Logic for ICE40PLLBlock<FIN_FREQ, FOUT_FREQ>

impl<const N: usize> Logic for DDR7FIFO<N>

impl<const N: usize> Logic for MuxedADS868XSimulators<N>

impl<const N: usize> Logic for PulseWidthModulator<N>

impl<const N: usize> Logic for Shot<N>

impl<const N: usize> Logic for SPIMaster<N>

impl<const N: usize> Logic for SPISlave<N>

impl<const N: usize> Logic for Strobe<N>

impl<const N: usize, const M: usize, const P: usize> Logic for Accum<N, M, P>