Struct rust_hdl::widgets::bidirectional_bus::FifoBus

pub struct FifoBus<T: Synth> {
    pub to_bus: Signal<In, T>,
    pub write: Signal<In, Bit>,
    pub full: Signal<Out, Bit>,
    pub from_bus: Signal<Out, T>,
    pub read: Signal<In, Bit>,
    pub empty: Signal<Out, Bit>,
}

Fields

to_bus: Signal<In, T>

write: Signal<In, Bit>

full: Signal<Out, Bit>

from_bus: Signal<Out, T>

read: Signal<In, Bit>

empty: Signal<Out, Bit>

Trait Implementations

impl<T: Synth> Block for FifoBus<T>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<T: Clone + Synth> Clone for FifoBus<T>

fn clone(&self) -> FifoBus<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Synth> Debug for FifoBus<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Default + Synth> Default for FifoBus<T>

fn default() -> FifoBus<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for FifoBus<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

impl<T: Synth> LogicLink for FifoBus<T>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(&self, my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>