[−][src]Struct msp432p401r::dma::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub dma_device_cfg: DMA_DEVICE_CFG,
    pub dma_sw_chtrig: DMA_SW_CHTRIG,
    pub dma_ch_srccfg: [DMA_CH_SRCCFG; 32],
    pub dma_int1_srccfg: DMA_INT1_SRCCFG,
    pub dma_int2_srccfg: DMA_INT2_SRCCFG,
    pub dma_int3_srccfg: DMA_INT3_SRCCFG,
    pub dma_int0_srcflg: DMA_INT0_SRCFLG,
    pub dma_int0_clrflg: DMA_INT0_CLRFLG,
    pub dma_stat: DMA_STAT,
    pub dma_cfg: DMA_CFG,
    pub dma_ctlbase: DMA_CTLBASE,
    pub dma_altbase: DMA_ALTBASE,
    pub dma_waitstat: DMA_WAITSTAT,
    pub dma_swreq: DMA_SWREQ,
    pub dma_useburstset: DMA_USEBURSTSET,
    pub dma_useburstclr: DMA_USEBURSTCLR,
    pub dma_reqmaskset: DMA_REQMASKSET,
    pub dma_reqmaskclr: DMA_REQMASKCLR,
    pub dma_enaset: DMA_ENASET,
    pub dma_enaclr: DMA_ENACLR,
    pub dma_altset: DMA_ALTSET,
    pub dma_altclr: DMA_ALTCLR,
    pub dma_prioset: DMA_PRIOSET,
    pub dma_prioclr: DMA_PRIOCLR,
    pub dma_errclr: DMA_ERRCLR,
    // some fields omitted
}

Register block

Fields

dma_device_cfg: DMA_DEVICE_CFG

0x00 - Device Configuration Status

dma_sw_chtrig: DMA_SW_CHTRIG

0x04 - Software Channel Trigger Register

dma_ch_srccfg: [DMA_CH_SRCCFG; 32]

0x10 - Channel n Source Configuration Register

dma_int1_srccfg: DMA_INT1_SRCCFG

0x100 - Interrupt 1 Source Channel Configuration

dma_int2_srccfg: DMA_INT2_SRCCFG

0x104 - Interrupt 2 Source Channel Configuration Register

dma_int3_srccfg: DMA_INT3_SRCCFG

0x108 - Interrupt 3 Source Channel Configuration Register

dma_int0_srcflg: DMA_INT0_SRCFLG

0x110 - Interrupt 0 Source Channel Flag Register

dma_int0_clrflg: DMA_INT0_CLRFLG

0x114 - Interrupt 0 Source Channel Clear Flag Register

dma_stat: DMA_STAT

0x1000 - Status Register

dma_cfg: DMA_CFG

0x1004 - Configuration Register

dma_ctlbase: DMA_CTLBASE

0x1008 - Channel Control Data Base Pointer Register

dma_altbase: DMA_ALTBASE

0x100c - Channel Alternate Control Data Base Pointer Register

dma_waitstat: DMA_WAITSTAT

0x1010 - Channel Wait on Request Status Register

dma_swreq: DMA_SWREQ

0x1014 - Channel Software Request Register

dma_useburstset: DMA_USEBURSTSET

0x1018 - Channel Useburst Set Register

dma_useburstclr: DMA_USEBURSTCLR

0x101c - Channel Useburst Clear Register

dma_reqmaskset: DMA_REQMASKSET

0x1020 - Channel Request Mask Set Register

dma_reqmaskclr: DMA_REQMASKCLR

0x1024 - Channel Request Mask Clear Register

dma_enaset: DMA_ENASET

0x1028 - Channel Enable Set Register

dma_enaclr: DMA_ENACLR

0x102c - Channel Enable Clear Register

dma_altset: DMA_ALTSET

0x1030 - Channel Primary-Alternate Set Register

dma_altclr: DMA_ALTCLR

0x1034 - Channel Primary-Alternate Clear Register

dma_prioset: DMA_PRIOSET

0x1038 - Channel Priority Set Register

dma_prioclr: DMA_PRIOCLR

0x103c - Channel Priority Clear Register

dma_errclr: DMA_ERRCLR

0x104c - Bus Error Clear Register

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