Struct lpc845_pac::adc0::inten::W [−][src]
pub struct W(_);
Expand description
Register INTEN
writer
Implementations
Bit 0 - Sequence A interrupt enable.
Bit 1 - Sequence B interrupt enable.
Bit 2 - Overrun interrupt enable.
Bits 3:4 - Threshold comparison interrupt enable for channel 0.
Bits 5:6 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
Bits 7:8 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
Bits 9:10 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
Bits 11:12 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
Bits 13:14 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
Bits 15:16 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
Bits 17:18 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
Bits 19:20 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
Bits 21:22 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
Bits 23:24 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
Bits 25:26 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
Methods from Deref<Target = W<INTEN_SPEC>>
Trait Implementations
Performs the conversion.