Module lpc845_pac::adc0::inten [−][src]
Expand description
ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
Structs
Field ADCMPINTEN0
reader - Threshold comparison interrupt enable for channel 0.
Field ADCMPINTEN0
writer - Threshold comparison interrupt enable for channel 0.
Field ADCMPINTEN1
reader - Channel 1 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN1
writer - Channel 1 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN2
reader - Channel 2 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN2
writer - Channel 2 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN3
reader - Channel 3 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN3
writer - Channel 3 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN4
reader - Channel 4 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN4
writer - Channel 4 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN5
reader - Channel 5 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN5
writer - Channel 5 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN6
reader - Channel 6 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN6
writer - Channel 6 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN7
reader - Channel 7 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN7
writer - Channel 7 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN8
reader - Channel 8 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN8
writer - Channel 8 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN9
reader - Channel 9 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN9
writer - Channel 9 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN10
reader - Channel 10 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN10
writer - Channel 10 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN11
reader - Channel 21 threshold comparison interrupt enable. See description for channel 0.
Field ADCMPINTEN11
writer - Channel 21 threshold comparison interrupt enable. See description for channel 0.
ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
Field OVR_INTEN
reader - Overrun interrupt enable.
Field OVR_INTEN
writer - Overrun interrupt enable.
Register INTEN
reader
Field SEQA_INTEN
reader - Sequence A interrupt enable.
Field SEQA_INTEN
writer - Sequence A interrupt enable.
Field SEQB_INTEN
reader - Sequence B interrupt enable.
Field SEQB_INTEN
writer - Sequence B interrupt enable.
Register INTEN
writer
Enums
Threshold comparison interrupt enable for channel 0.
Overrun interrupt enable.
Sequence A interrupt enable.
Sequence B interrupt enable.