Module lpc845_pac::adc0::inten[−][src]

Expand description

ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

Structs

ADCMPINTEN0_R

Field ADCMPINTEN0 reader - Threshold comparison interrupt enable for channel 0.

ADCMPINTEN0_W

Field ADCMPINTEN0 writer - Threshold comparison interrupt enable for channel 0.

ADCMPINTEN1_R

Field ADCMPINTEN1 reader - Channel 1 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN1_W

Field ADCMPINTEN1 writer - Channel 1 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN2_R

Field ADCMPINTEN2 reader - Channel 2 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN2_W

Field ADCMPINTEN2 writer - Channel 2 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN3_R

Field ADCMPINTEN3 reader - Channel 3 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN3_W

Field ADCMPINTEN3 writer - Channel 3 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN4_R

Field ADCMPINTEN4 reader - Channel 4 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN4_W

Field ADCMPINTEN4 writer - Channel 4 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN5_R

Field ADCMPINTEN5 reader - Channel 5 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN5_W

Field ADCMPINTEN5 writer - Channel 5 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN6_R

Field ADCMPINTEN6 reader - Channel 6 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN6_W

Field ADCMPINTEN6 writer - Channel 6 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN7_R

Field ADCMPINTEN7 reader - Channel 7 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN7_W

Field ADCMPINTEN7 writer - Channel 7 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN8_R

Field ADCMPINTEN8 reader - Channel 8 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN8_W

Field ADCMPINTEN8 writer - Channel 8 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN9_R

Field ADCMPINTEN9 reader - Channel 9 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN9_W

Field ADCMPINTEN9 writer - Channel 9 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN10_R

Field ADCMPINTEN10 reader - Channel 10 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN10_W

Field ADCMPINTEN10 writer - Channel 10 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN11_R

Field ADCMPINTEN11 reader - Channel 21 threshold comparison interrupt enable. See description for channel 0.

ADCMPINTEN11_W

Field ADCMPINTEN11 writer - Channel 21 threshold comparison interrupt enable. See description for channel 0.

INTEN_SPEC

ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

OVR_INTEN_R

Field OVR_INTEN reader - Overrun interrupt enable.

OVR_INTEN_W

Field OVR_INTEN writer - Overrun interrupt enable.

R

Register INTEN reader

SEQA_INTEN_R

Field SEQA_INTEN reader - Sequence A interrupt enable.

SEQA_INTEN_W

Field SEQA_INTEN writer - Sequence A interrupt enable.

SEQB_INTEN_R

Field SEQB_INTEN reader - Sequence B interrupt enable.