Module lpc845_pac::adc0[−][src]

Expand description

LPC84x 12-bit ADC controller (ADC)

Modules

ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel

ctrl

ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.

dat

ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.

flags

ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).

inten

ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.

seq_ctrl

ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

seq_gdat

ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.

thr0_high

ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr0_low

ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.

thr1_high

ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

thr1_low

ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.

trm

ADC Startup register.