Enum lpc845_pac::adc0::inten::OVR_INTEN_A [−][src]
pub enum OVR_INTEN_A {
DISABLED,
ENABLED,
}
Expand description
Overrun interrupt enable.
Value on reset: 0
Variants
0: Disabled. The overrun interrupt is disabled.
1: Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.
Trait Implementations
Performs the conversion.