Struct lpc845_pac::adc0::inten::W

pub struct W(_);

Register INTEN writer

Implementations

impl W

pub fn seqa_inten(&mut self) -> SEQA_INTEN_W<'_>

Bit 0 - Sequence A interrupt enable.

pub fn seqb_inten(&mut self) -> SEQB_INTEN_W<'_>

Bit 1 - Sequence B interrupt enable.

pub fn ovr_inten(&mut self) -> OVR_INTEN_W<'_>

Bit 2 - Overrun interrupt enable.

pub fn adcmpinten0(&mut self) -> ADCMPINTEN0_W<'_>

Bits 3:4 - Threshold comparison interrupt enable for channel 0.

pub fn adcmpinten1(&mut self) -> ADCMPINTEN1_W<'_>

Bits 5:6 - Channel 1 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten2(&mut self) -> ADCMPINTEN2_W<'_>

Bits 7:8 - Channel 2 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten3(&mut self) -> ADCMPINTEN3_W<'_>

Bits 9:10 - Channel 3 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten4(&mut self) -> ADCMPINTEN4_W<'_>

Bits 11:12 - Channel 4 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten5(&mut self) -> ADCMPINTEN5_W<'_>

Bits 13:14 - Channel 5 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten6(&mut self) -> ADCMPINTEN6_W<'_>

Bits 15:16 - Channel 6 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten7(&mut self) -> ADCMPINTEN7_W<'_>

Bits 17:18 - Channel 7 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten8(&mut self) -> ADCMPINTEN8_W<'_>

Bits 19:20 - Channel 8 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten9(&mut self) -> ADCMPINTEN9_W<'_>

Bits 21:22 - Channel 9 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten10(&mut self) -> ADCMPINTEN10_W<'_>

Bits 23:24 - Channel 10 threshold comparison interrupt enable. See description for channel 0.

pub fn adcmpinten11(&mut self) -> ADCMPINTEN11_W<'_>

Bits 25:26 - Channel 21 threshold comparison interrupt enable. See description for channel 0.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INTEN_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTEN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INTEN_SPEC>> for W

fn from(writer: W<INTEN_SPEC>) -> Self

Performs the conversion.