[−][src]Struct lpc54606_pac::syscon::RegisterBlock
Register block
Fields
ahbmatprio: AHBMATPRIO0x10 - AHB multilayer matrix priority control
systckcal: SYSTCKCAL0x40 - System tick counter calibration
nmisrc: NMISRC0x48 - NMI Source Select
asyncapbctrl: ASYNCAPBCTRL0x4c - Asynchronous APB Control
pioporcap: [PIOPORCAP; 2]0xc0 - POR captured value of port n
piorescap: [PIORESCAP; 2]0xd0 - Reset captured value of port n
presetctrl0: PRESETCTRL00x100 - Peripheral reset control n
presetctrl1: PRESETCTRL10x104 - Peripheral reset control n
presetctrl2: PRESETCTRL20x108 - Peripheral reset control n
presetctrlset: [PRESETCTRLSET; 3]0x120 - Set bits in PRESETCTRLn
presetctrlclr: [PRESETCTRLCLR; 3]0x140 - Clear bits in PRESETCTRLn
sysrststat: SYSRSTSTAT0x1f0 - System reset status register
ahbclkctrl0: AHBCLKCTRL00x200 - AHB Clock control n
ahbclkctrl1: AHBCLKCTRL10x204 - AHB Clock control n
ahbclkctrl2: AHBCLKCTRL20x208 - AHB Clock control n
ahbclkctrlset: [AHBCLKCTRLSET; 3]0x220 - Set bits in AHBCLKCTRLn
ahbclkctrlclr: [AHBCLKCTRLCLR; 3]0x240 - Clear bits in AHBCLKCTRLn
mainclksela: MAINCLKSELA0x280 - Main clock source select A
mainclkselb: MAINCLKSELB0x284 - Main clock source select B
clkoutsela: CLKOUTSELA0x288 - CLKOUT clock source select A
syspllclksel: SYSPLLCLKSEL0x290 - PLL clock source select
audpllclksel: AUDPLLCLKSEL0x298 - Audio PLL clock source select
spificlksel: SPIFICLKSEL0x2a0 - SPIFI clock source select
adcclksel: ADCCLKSEL0x2a4 - ADC clock source select
usb0clksel: USB0CLKSEL0x2a8 - USB0 clock source select
usb1clksel: USB1CLKSEL0x2ac - USB1 clock source select
fclksel: [FCLKSEL; 10]0x2b0 - Flexcomm 0 clock source select
mclkclksel: MCLKCLKSEL0x2e0 - MCLK clock source select
frgclksel: FRGCLKSEL0x2e8 - Fractional Rate Generator clock source select
dmicclksel: DMICCLKSEL0x2ec - Digital microphone (DMIC) subsystem clock select
sctclksel: SCTCLKSEL0x2f0 - SCTimer/PWM clock source select
lcdclksel: LCDCLKSEL0x2f4 - LCD clock source select
sdioclksel: SDIOCLKSEL0x2f8 - SDIO clock source select
systickclkdiv: SYSTICKCLKDIV0x300 - SYSTICK clock divider
armtraceclkdiv: ARMTRACECLKDIV0x304 - ARM Trace clock divider
can0clkdiv: CAN0CLKDIV0x308 - MCAN0 clock divider
can1clkdiv: CAN1CLKDIV0x30c - MCAN1 clock divider
sc0clkdiv: SC0CLKDIV0x310 - Smartcard0 clock divider
sc1clkdiv: SC1CLKDIV0x314 - Smartcard1 clock divider
ahbclkdiv: AHBCLKDIV0x380 - AHB clock divider
clkoutdiv: CLKOUTDIV0x384 - CLKOUT clock divider
frohfclkdiv: FROHFCLKDIV0x388 - FROHF clock divider
spificlkdiv: SPIFICLKDIV0x390 - SPIFI clock divider
adcclkdiv: ADCCLKDIV0x394 - ADC clock divider
usb0clkdiv: USB0CLKDIV0x398 - USB0 clock divider
usb1clkdiv: USB1CLKDIV0x39c - USB1 clock divider
frgctrl: FRGCTRL0x3a0 - Fractional rate divider
dmicclkdiv: DMICCLKDIV0x3a8 - DMIC clock divider
mclkdiv: MCLKDIV0x3ac - I2S MCLK clock divider
lcdclkdiv: LCDCLKDIV0x3b0 - LCD clock divider
sctclkdiv: SCTCLKDIV0x3b4 - SCT/PWM clock divider
emcclkdiv: EMCCLKDIV0x3b8 - EMC clock divider
sdioclkdiv: SDIOCLKDIV0x3bc - SDIO clock divider
flashcfg: FLASHCFG0x400 - Flash wait states configuration
usb0clkctrl: USB0CLKCTRL0x40c - USB0 clock control
usb0clkstat: USB0CLKSTAT0x410 - USB0 clock status
freqmectrl: FREQMECTRL0x418 - Frequency measure register
mclkio: MCLKIO0x420 - MCLK input/output control
usb1clkctrl: USB1CLKCTRL0x424 - USB1 clock control
usb1clkstat: USB1CLKSTAT0x428 - USB1 clock status
emcsysctrl: EMCSYSCTRL0x444 - EMC system control
emcdlyctrl: EMCDLYCTRL0x448 - EMC clock delay control
emcdlycal: EMCDLYCAL0x44c - EMC delay chain calibration control
ethphysel: ETHPHYSEL0x450 - Ethernet PHY Selection
ethsbdctrl: ETHSBDCTRL0x454 - Ethernet SBD flow control
sdioclkctrl: SDIOCLKCTRL0x460 - SDIO CCLKIN phase and delay control
froctrl: FROCTRL0x500 - FRO oscillator control
sysoscctrl: SYSOSCCTRL0x504 - System oscillator control
wdtoscctrl: WDTOSCCTRL0x508 - Watchdog oscillator control
rtcoscctrl: RTCOSCCTRL0x50c - RTC oscillator 32 kHz output control
usbpllctrl: USBPLLCTRL0x51c - USB PLL control
usbpllstat: USBPLLSTAT0x520 - USB PLL status
syspllctrl: SYSPLLCTRL0x580 - System PLL control
syspllstat: SYSPLLSTAT0x584 - PLL status
syspllndec: SYSPLLNDEC0x588 - PLL N divider
syspllpdec: SYSPLLPDEC0x58c - PLL P divider
syspllmdec: SYSPLLMDEC0x590 - System PLL M divider
audpllctrl: AUDPLLCTRL0x5a0 - Audio PLL control
audpllstat: AUDPLLSTAT0x5a4 - Audio PLL status
audpllndec: AUDPLLNDEC0x5a8 - Audio PLL N divider
audpllpdec: AUDPLLPDEC0x5ac - Audio PLL P divider
audpllmdec: AUDPLLMDEC0x5b0 - Audio PLL M divider
audpllfrac: AUDPLLFRAC0x5b4 - Audio PLL fractional divider control
pdsleepcfg0: PDSLEEPCFG00x600 - Sleep configuration register
pdsleepcfg1: PDSLEEPCFG10x604 - Sleep configuration register
pdruncfg0: PDRUNCFG00x610 - Power configuration register
pdruncfg1: PDRUNCFG10x614 - Power configuration register
pdruncfgset0: PDRUNCFGSET00x620 - Power configuration set register
pdruncfgset1: PDRUNCFGSET10x624 - Power configuration set register
pdruncfgclr0: PDRUNCFGCLR00x630 - Power configuration clear register
pdruncfgclr1: PDRUNCFGCLR10x634 - Power configuration clear register
starter0: STARTER00x680 - Start logic 0 wake-up enable register
starter1: STARTER10x684 - Start logic 0 wake-up enable register
starterset: [STARTERSET; 2]0x6a0 - Set bits in STARTER
starterclr: [STARTERCLR; 2]0x6c0 - Clear bits in STARTER0
hwwake: HWWAKE0x780 - Configures special cases of hardware wake-up
autocgor: AUTOCGOR0xe04 - Auto Clock-Gate Override Register
jtagidcode: JTAGIDCODE0xff4 - JTAG ID code register
device_id0: DEVICE_ID00xff8 - Part ID register
device_id1: DEVICE_ID10xffc - Boot ROM and die revision register
bodctrl: BODCTRL0x20044 - Brown-Out Detect control
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