[][src]Type Definition lpc54606_pac::syscon::CAN1CLKDIV

type CAN1CLKDIV = Reg<u32, _CAN1CLKDIV>;

MCAN1 clock divider

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see can1clkdiv module

Trait Implementations

impl Readable for CAN1CLKDIV[src]

read() method returns can1clkdiv::R reader structure

impl ResetValue for CAN1CLKDIV[src]

Register CAN1CLKDIV reset()'s with value 0x4000_0000

type Type = u32

Register size

impl Writable for CAN1CLKDIV[src]

write(|w| ..) method takes can1clkdiv::W writer structure