Type Alias esp32c3::spi2::user::W

pub type W = W<USER_SPEC>;

Register USER writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn doutdin(&mut self) -> DOUTDIN_W<'_, USER_SPEC>

Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.

pub fn qpi_mode(&mut self) -> QPI_MODE_W<'_, USER_SPEC>

Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.

pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<'_, USER_SPEC>

Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.

pub fn cs_hold(&mut self) -> CS_HOLD_W<'_, USER_SPEC>

Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn cs_setup(&mut self) -> CS_SETUP_W<'_, USER_SPEC>

Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<'_, USER_SPEC>

Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.

pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<'_, USER_SPEC>

Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.

pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<'_, USER_SPEC>

Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state.

pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<'_, USER_SPEC>

Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state.

pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<'_, USER_SPEC>

Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.

pub fn sio(&mut self) -> SIO_W<'_, USER_SPEC>

Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<'_, USER_SPEC>

Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<'_, USER_SPEC>

Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<'_, USER_SPEC>

Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.

pub fn usr_mosi(&mut self) -> USR_MOSI_W<'_, USER_SPEC>

Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state.

pub fn usr_miso(&mut self) -> USR_MISO_W<'_, USER_SPEC>

Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state.

pub fn usr_dummy(&mut self) -> USR_DUMMY_W<'_, USER_SPEC>

Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state.

pub fn usr_addr(&mut self) -> USR_ADDR_W<'_, USER_SPEC>

Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state.

pub fn usr_command(&mut self) -> USR_COMMAND_W<'_, USER_SPEC>

Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state.