Module esp32c3::spi2::user

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SPI USER control register

Structs§

Type Aliases§

  • CK_OUT_EDGE_R
    Field CK_OUT_EDGE reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
  • CK_OUT_EDGE_W
    Field CK_OUT_EDGE writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
  • CS_HOLD_R
    Field CS_HOLD reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
  • CS_HOLD_W
    Field CS_HOLD writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
  • CS_SETUP_R
    Field CS_SETUP reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
  • CS_SETUP_W
    Field CS_SETUP writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
  • DOUTDIN_R
    Field DOUTDIN reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
  • DOUTDIN_W
    Field DOUTDIN writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
  • FWRITE_DUAL_R
    Field FWRITE_DUAL reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
  • FWRITE_DUAL_W
    Field FWRITE_DUAL writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
  • FWRITE_QUAD_R
    Field FWRITE_QUAD reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
  • FWRITE_QUAD_W
    Field FWRITE_QUAD writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
  • QPI_MODE_R
    Field QPI_MODE reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
  • QPI_MODE_W
    Field QPI_MODE writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
  • R
    Register USER reader
  • RSCK_I_EDGE_R
    Field RSCK_I_EDGE reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
  • RSCK_I_EDGE_W
    Field RSCK_I_EDGE writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
  • SIO_R
    Field SIO reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
  • SIO_W
    Field SIO writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
  • TSCK_I_EDGE_R
    Field TSCK_I_EDGE reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
  • TSCK_I_EDGE_W
    Field TSCK_I_EDGE writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
  • USR_ADDR_R
    Field USR_ADDR reader - This bit enable the address phase of an operation. Can be configured in CONF state.
  • USR_ADDR_W
    Field USR_ADDR writer - This bit enable the address phase of an operation. Can be configured in CONF state.
  • USR_COMMAND_R
    Field USR_COMMAND reader - This bit enable the command phase of an operation. Can be configured in CONF state.
  • USR_COMMAND_W
    Field USR_COMMAND writer - This bit enable the command phase of an operation. Can be configured in CONF state.
  • USR_CONF_NXT_R
    Field USR_CONF_NXT reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
  • USR_CONF_NXT_W
    Field USR_CONF_NXT writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
  • USR_DUMMY_IDLE_R
    Field USR_DUMMY_IDLE reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
  • USR_DUMMY_IDLE_W
    Field USR_DUMMY_IDLE writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
  • USR_DUMMY_R
    Field USR_DUMMY reader - This bit enable the dummy phase of an operation. Can be configured in CONF state.
  • USR_DUMMY_W
    Field USR_DUMMY writer - This bit enable the dummy phase of an operation. Can be configured in CONF state.
  • USR_MISO_HIGHPART_R
    Field USR_MISO_HIGHPART reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
  • USR_MISO_HIGHPART_W
    Field USR_MISO_HIGHPART writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
  • USR_MISO_R
    Field USR_MISO reader - This bit enable the read-data phase of an operation. Can be configured in CONF state.
  • USR_MISO_W
    Field USR_MISO writer - This bit enable the read-data phase of an operation. Can be configured in CONF state.
  • USR_MOSI_HIGHPART_R
    Field USR_MOSI_HIGHPART reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
  • USR_MOSI_HIGHPART_W
    Field USR_MOSI_HIGHPART writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
  • USR_MOSI_R
    Field USR_MOSI reader - This bit enable the write-data phase of an operation. Can be configured in CONF state.
  • USR_MOSI_W
    Field USR_MOSI writer - This bit enable the write-data phase of an operation. Can be configured in CONF state.
  • W
    Register USER writer