Type Alias esp32c3::spi2::misc::W

pub type W = W<MISC_SPEC>;

Register MISC writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn cs0_dis(&mut self) -> CS0_DIS_W<'_, MISC_SPEC>

Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.

pub fn cs1_dis(&mut self) -> CS1_DIS_W<'_, MISC_SPEC>

Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.

pub fn cs2_dis(&mut self) -> CS2_DIS_W<'_, MISC_SPEC>

Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.

pub fn cs3_dis(&mut self) -> CS3_DIS_W<'_, MISC_SPEC>

Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.

pub fn cs4_dis(&mut self) -> CS4_DIS_W<'_, MISC_SPEC>

Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.

pub fn cs5_dis(&mut self) -> CS5_DIS_W<'_, MISC_SPEC>

Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.

pub fn ck_dis(&mut self) -> CK_DIS_W<'_, MISC_SPEC>

Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<'_, MISC_SPEC>

Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.

pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<'_, MISC_SPEC>

Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<'_, MISC_SPEC>

Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<'_, MISC_SPEC>

Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state.

pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<'_, MISC_SPEC>

Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.