Type Alias esp32c3::spi2::din_mode::W

pub type W = W<DIN_MODE_SPEC>;

Register DIN_MODE writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn din0_mode(&mut self) -> DIN0_MODE_W<'_, DIN_MODE_SPEC>

Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din1_mode(&mut self) -> DIN1_MODE_W<'_, DIN_MODE_SPEC>

Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din2_mode(&mut self) -> DIN2_MODE_W<'_, DIN_MODE_SPEC>

Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din3_mode(&mut self) -> DIN3_MODE_W<'_, DIN_MODE_SPEC>

Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<'_, DIN_MODE_SPEC>

Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.