Module esp32c3::spi2::din_mode

SPI input delay mode configuration

Structs

• DIN_MODE_SPEC
  SPI input delay mode configuration

Type Aliases

• DIN0_MODE_R
  Field DIN0_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN0_MODE_W
  Field DIN0_MODE writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN1_MODE_R
  Field DIN1_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN1_MODE_W
  Field DIN1_MODE writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN2_MODE_R
  Field DIN2_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN2_MODE_W
  Field DIN2_MODE writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN3_MODE_R
  Field DIN3_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• DIN3_MODE_W
  Field DIN3_MODE writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
• R
  Register DIN_MODE reader
• TIMING_HCLK_ACTIVE_R
  Field TIMING_HCLK_ACTIVE reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
• TIMING_HCLK_ACTIVE_W
  Field TIMING_HCLK_ACTIVE writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
• W
  Register DIN_MODE writer