Struct esp32c2_hal::pac::spi1::int_raw::R
pub struct R(_);
Expand description
Register INT_RAW
reader
Implementations§
§impl R
impl R
pub fn per_end_int_raw(&self) -> BitReaderRaw<bool>
pub fn per_end_int_raw(&self) -> BitReaderRaw<bool>
Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
pub fn pes_end_int_raw(&self) -> BitReaderRaw<bool>
pub fn pes_end_int_raw(&self) -> BitReaderRaw<bool>
Bit 1 - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
pub fn wpe_end_int_raw(&self) -> BitReaderRaw<bool>
pub fn wpe_end_int_raw(&self) -> BitReaderRaw<bool>
Bit 2 - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
pub fn slv_st_end_int_raw(&self) -> BitReaderRaw<bool>
pub fn slv_st_end_int_raw(&self) -> BitReaderRaw<bool>
Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
pub fn mst_st_end_int_raw(&self) -> BitReaderRaw<bool>
pub fn mst_st_end_int_raw(&self) -> BitReaderRaw<bool>
Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
pub fn brown_out_int_raw(&self) -> BitReaderRaw<bool>
pub fn brown_out_int_raw(&self) -> BitReaderRaw<bool>
Bit 5 - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.
Methods from Deref<Target = R<INT_RAW_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.