Struct esp32c2_hal::pac::spi1::flash_sus_ctrl::R
pub struct R(_);Expand description
Register FLASH_SUS_CTRL reader
Implementations§
§impl R
impl R
pub fn flash_per(&self) -> BitReaderRaw<bool>
pub fn flash_per(&self) -> BitReaderRaw<bool>
Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
pub fn flash_pes(&self) -> BitReaderRaw<bool>
pub fn flash_pes(&self) -> BitReaderRaw<bool>
Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
pub fn flash_per_wait_en(&self) -> BitReaderRaw<bool>
pub fn flash_per_wait_en(&self) -> BitReaderRaw<bool>
Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
pub fn flash_pes_wait_en(&self) -> BitReaderRaw<bool>
pub fn flash_pes_wait_en(&self) -> BitReaderRaw<bool>
Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
pub fn pes_per_en(&self) -> BitReaderRaw<bool>
pub fn pes_per_en(&self) -> BitReaderRaw<bool>
Bit 4 - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
pub fn flash_pes_en(&self) -> BitReaderRaw<bool>
pub fn flash_pes_en(&self) -> BitReaderRaw<bool>
Bit 5 - Set this bit to enable Auto-suspending function.
pub fn pesr_end_msk(&self) -> FieldReaderRaw<u16, u16>
pub fn pesr_end_msk(&self) -> FieldReaderRaw<u16, u16>
Bits 6:21 - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
pub fn spi_fmem_rd_sus_2b(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_rd_sus_2b(&self) -> BitReaderRaw<bool>
Bit 22 - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit
pub fn per_end_en(&self) -> BitReaderRaw<bool>
pub fn per_end_en(&self) -> BitReaderRaw<bool>
Bit 23 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
pub fn pes_end_en(&self) -> BitReaderRaw<bool>
pub fn pes_end_en(&self) -> BitReaderRaw<bool>
Bit 24 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
pub fn sus_timeout_cnt(&self) -> FieldReaderRaw<u8, u8>
pub fn sus_timeout_cnt(&self) -> FieldReaderRaw<u8, u8>
Bits 25:31 - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
Methods from Deref<Target = R<FLASH_SUS_CTRL_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.