Module esp32c2_hal::pac::spi1::flash_sus_ctrl
Expand description
SPI1 flash suspend control register
Structs
SPI1 flash suspend control register
Register
FLASH_SUS_CTRL
readerRegister
FLASH_SUS_CTRL
writerType Definitions
Field
FLASH_PER
reader - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.Field
FLASH_PER
writer - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.Field
FLASH_PER_WAIT_EN
reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.Field
FLASH_PER_WAIT_EN
writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.Field
FLASH_PES_EN
reader - Set this bit to enable Auto-suspending function.Field
FLASH_PES_EN
writer - Set this bit to enable Auto-suspending function.Field
FLASH_PES
reader - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.Field
FLASH_PES
writer - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.Field
FLASH_PES_WAIT_EN
reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.Field
FLASH_PES_WAIT_EN
writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.Field
PER_END_EN
reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.Field
PER_END_EN
writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.Field
PESR_END_MSK
reader - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].Field
PESR_END_MSK
writer - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].Field
PES_END_EN
reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.Field
PES_END_EN
writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.Field
PES_PER_EN
reader - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.Field
PES_PER_EN
writer - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.Field
SPI_FMEM_RD_SUS_2B
reader - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bitField
SPI_FMEM_RD_SUS_2B
writer - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bitField
SUS_TIMEOUT_CNT
reader - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.Field
SUS_TIMEOUT_CNT
writer - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.