Struct RegisterBlock 

#[repr(C)]
pub struct RegisterBlock {

    pub ctrlr1: Reg<CTRLR1_SPEC>,
    pub ssienr: Reg<SSIENR_SPEC>,
    pub ser: Reg<SER_SPEC>,
    pub baudr: Reg<BAUDR_SPEC>,
    pub txftlr: Reg<TXFTLR_SPEC>,
    pub rxftlr: Reg<RXFTLR_SPEC>,
    pub txflr: Reg<TXFLR_SPEC>,
    pub rxflr: Reg<RXFLR_SPEC>,
    pub sr: Reg<SR_SPEC>,
    pub imr: Reg<IMR_SPEC>,
    pub isr: Reg<ISR_SPEC>,
    pub risr: Reg<RISR_SPEC>,
    pub txoicr: Reg<TXOICR_SPEC>,
    pub rxoicr: Reg<RXOICR_SPEC>,
    pub rxuicr: Reg<RXUICR_SPEC>,
    pub msticr: Reg<MSTICR_SPEC>,
    pub icr: Reg<ICR_SPEC>,
    pub idr: Reg<IDR_SPEC>,
    pub ssi_comp_version: Reg<SSI_COMP_VERSION_SPEC>,
    /* private fields */
}

Register block

Fields

ctrlr1: Reg<CTRLR1_SPEC>

0x04 - Control Register 1: CTRLR1 register controls the end of serial transfers when in receive-only mode. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008).

ssienr: Reg<SSIENR_SPEC>

0x08 - SSI Enable Register: This register enables and disables the SPI Master. The following SPI Master registers are NOT writeable when SPI Master is enabled =1: CTRLR0, CTRLR1, BAUDR. You must set SSIENR = 0, before writing these 3 registers. The following SPI Master registers are writeable ONLY when the SPI Master is enabled = 1: DR0.

ser: Reg<SER_SPEC>

0x10 - Slave Enable Register: This register enables the individual slave select output lines from the SPI Master. You cannot write to this register when SPI Master is busy.

baudr: Reg<BAUDR_SPEC>

0x14 - Baud Rate Select Register: This register derives the frequency of the serial clock that regulates the data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing the SSIENR register (0x008).

txftlr: Reg<TXFTLR_SPEC>

0x18 - Transmit FFIFO Threshold Level Register: This register controls the threshold value for the transmit FIFO memory.

rxftlr: Reg<RXFTLR_SPEC>

0x1c - Receive FIFO Threshold Level Register: This register controls the threshold value for the receive FIFO memory.

txflr: Reg<TXFLR_SPEC>

0x20 - Transmit FIFO Level Register: This register contains the number of valid data entries in the transmit FIFO memory.

rxflr: Reg<RXFLR_SPEC>

0x24 - Receive FIFO Level Register: This register contains the number of valid data entries in FIFO memory. This register can be read at any time.

sr: Reg<SR_SPEC>

0x28 - Status Register: This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. This status register may be read at any time. None of the bits in this register request an interrupt.

imr: Reg<IMR_SPEC>

0x2c - Interrupt Mask Register: This read/write register masks or enables all interrupts generated by the SPI Master.

isr: Reg<ISR_SPEC>

0x30 - Interrupt Status Register: This register reports the status of SPI Master interrupts after they have been masked.

risr: Reg<RISR_SPEC>

0x34 - Raw Interrupt Status Register: This read-only register reports the status of the SPI Master interrupts prior to masking.

txoicr: Reg<TXOICR_SPEC>

0x38 - Transmit FIFO Overflow Interrupt Clear Register.

rxoicr: Reg<RXOICR_SPEC>

0x3c - Receive FIFO Overflow Interrupt Clear Register.

rxuicr: Reg<RXUICR_SPEC>

0x40 - Receive FIFO Underflow Interrupt Clear Register.

msticr: Reg<MSTICR_SPEC>

0x44 - Multi-Master Interrupt Clear Register.

icr: Reg<ICR_SPEC>

0x48 - Interrupt Clear Register.

idr: Reg<IDR_SPEC>

0x58 - Identification Code. This register contains the peripherals identification code.

ssi_comp_version: Reg<SSI_COMP_VERSION_SPEC>

0x5c - Contains the hex representation of the component version. Consists of ASCII value for each number in the version, followed by . For example 32_30_31_2A represents the version 2.01.

Implementations

impl RegisterBlock

pub fn dr0(&self) -> &Reg<DR0_SPEC>

0x00 - The SPI Master data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. Please refer to SSIENR register (0x008) to enable and disable the SPI Master. The DR register in the SPI Master occupies 131(for TX)/8(for RX) 32-bit address locations of the memory map to facilitate AHB burst transfers. Writing to any of these address locations has the same effect as pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI Master are not addressable.

pub fn ctrlr0(&self) -> &Reg<CTRLR0_SPEC>

0x00 - Control Register 0: This register controls the serial data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008).