1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved_0_dr0: [u8; 0x04],
5 #[doc = "0x04 - Control Register 1: CTRLR1 register controls the end of serial transfers when in receive-only mode. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008)."]
6 pub ctrlr1: crate::Reg<ctrlr1::CTRLR1_SPEC>,
7 _reserved2: [u8; 0x02],
8 #[doc = "0x08 - SSI Enable Register: This register enables and disables the SPI Master. The following SPI Master registers are NOT writeable when SPI Master is enabled =1: CTRLR0, CTRLR1, BAUDR. You must set SSIENR = 0, before writing these 3 registers. The following SPI Master registers are writeable ONLY when the SPI Master is enabled = 1: DR0."]
9 pub ssienr: crate::Reg<ssienr::SSIENR_SPEC>,
10 _reserved3: [u8; 0x07],
11 #[doc = "0x10 - Slave Enable Register: This register enables the individual slave select output lines from the SPI Master. You cannot write to this register when SPI Master is busy."]
12 pub ser: crate::Reg<ser::SER_SPEC>,
13 _reserved4: [u8; 0x03],
14 #[doc = "0x14 - Baud Rate Select Register: This register derives the frequency of the serial clock that regulates the data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing the SSIENR register (0x008)."]
15 pub baudr: crate::Reg<baudr::BAUDR_SPEC>,
16 _reserved5: [u8; 0x02],
17 #[doc = "0x18 - Transmit FFIFO Threshold Level Register: This register controls the threshold value for the transmit FIFO memory."]
18 pub txftlr: crate::Reg<txftlr::TXFTLR_SPEC>,
19 #[doc = "0x1c - Receive FIFO Threshold Level Register: This register controls the threshold value for the receive FIFO memory."]
20 pub rxftlr: crate::Reg<rxftlr::RXFTLR_SPEC>,
21 #[doc = "0x20 - Transmit FIFO Level Register: This register contains the number of valid data entries in the transmit FIFO memory."]
22 pub txflr: crate::Reg<txflr::TXFLR_SPEC>,
23 #[doc = "0x24 - Receive FIFO Level Register: This register contains the number of valid data entries in FIFO memory. This register can be read at any time."]
24 pub rxflr: crate::Reg<rxflr::RXFLR_SPEC>,
25 #[doc = "0x28 - Status Register: This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. This status register may be read at any time. None of the bits in this register request an interrupt."]
26 pub sr: crate::Reg<sr::SR_SPEC>,
27 _reserved10: [u8; 0x03],
28 #[doc = "0x2c - Interrupt Mask Register: This read/write register masks or enables all interrupts generated by the SPI Master."]
29 pub imr: crate::Reg<imr::IMR_SPEC>,
30 #[doc = "0x30 - Interrupt Status Register: This register reports the status of SPI Master interrupts after they have been masked."]
31 pub isr: crate::Reg<isr::ISR_SPEC>,
32 #[doc = "0x34 - Raw Interrupt Status Register: This read-only register reports the status of the SPI Master interrupts prior to masking."]
33 pub risr: crate::Reg<risr::RISR_SPEC>,
34 #[doc = "0x38 - Transmit FIFO Overflow Interrupt Clear Register."]
35 pub txoicr: crate::Reg<txoicr::TXOICR_SPEC>,
36 _reserved14: [u8; 0x03],
37 #[doc = "0x3c - Receive FIFO Overflow Interrupt Clear Register."]
38 pub rxoicr: crate::Reg<rxoicr::RXOICR_SPEC>,
39 _reserved15: [u8; 0x03],
40 #[doc = "0x40 - Receive FIFO Underflow Interrupt Clear Register."]
41 pub rxuicr: crate::Reg<rxuicr::RXUICR_SPEC>,
42 _reserved16: [u8; 0x03],
43 #[doc = "0x44 - Multi-Master Interrupt Clear Register."]
44 pub msticr: crate::Reg<msticr::MSTICR_SPEC>,
45 _reserved17: [u8; 0x03],
46 #[doc = "0x48 - Interrupt Clear Register."]
47 pub icr: crate::Reg<icr::ICR_SPEC>,
48 _reserved18: [u8; 0x0f],
49 #[doc = "0x58 - Identification Code. This register contains the peripherals identification code."]
50 pub idr: crate::Reg<idr::IDR_SPEC>,
51 #[doc = "0x5c - Contains the hex representation of the component version. Consists of ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01*."]
52 pub ssi_comp_version: crate::Reg<ssi_comp_version::SSI_COMP_VERSION_SPEC>,
53}
54impl RegisterBlock {
55 #[doc = "0x00 - The SPI Master data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. Please refer to SSIENR register (0x008) to enable and disable the SPI Master. The DR register in the SPI Master occupies 131(for TX)/8(for RX) 32-bit address locations of the memory map to facilitate AHB burst transfers. Writing to any of these address locations has the same effect as pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI Master are not addressable."]
56 #[inline(always)]
57 pub fn dr0(&self) -> &crate::Reg<dr0::DR0_SPEC> {
58 unsafe {
59 &*(((self as *const Self) as *const u8).add(0usize)
60 as *const crate::Reg<dr0::DR0_SPEC>)
61 }
62 }
63 #[doc = "0x00 - Control Register 0: This register controls the serial data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008)."]
64 #[inline(always)]
65 pub fn ctrlr0(&self) -> &crate::Reg<ctrlr0::CTRLR0_SPEC> {
66 unsafe {
67 &*(((self as *const Self) as *const u8).add(0usize)
68 as *const crate::Reg<ctrlr0::CTRLR0_SPEC>)
69 }
70 }
71}
72#[doc = "CTRLR0 register accessor: an alias for `Reg<CTRLR0_SPEC>`"]
73pub type CTRLR0 = crate::Reg<ctrlr0::CTRLR0_SPEC>;
74#[doc = "Control Register 0: This register controls the serial data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008)."]
75pub mod ctrlr0;
76#[doc = "CTRLR1 register accessor: an alias for `Reg<CTRLR1_SPEC>`"]
77pub type CTRLR1 = crate::Reg<ctrlr1::CTRLR1_SPEC>;
78#[doc = "Control Register 1: CTRLR1 register controls the end of serial transfers when in receive-only mode. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008)."]
79pub mod ctrlr1;
80#[doc = "SSIENR register accessor: an alias for `Reg<SSIENR_SPEC>`"]
81pub type SSIENR = crate::Reg<ssienr::SSIENR_SPEC>;
82#[doc = "SSI Enable Register: This register enables and disables the SPI Master. The following SPI Master registers are NOT writeable when SPI Master is enabled =1: CTRLR0, CTRLR1, BAUDR. You must set SSIENR = 0, before writing these 3 registers. The following SPI Master registers are writeable ONLY when the SPI Master is enabled = 1: DR0."]
83pub mod ssienr;
84#[doc = "SER register accessor: an alias for `Reg<SER_SPEC>`"]
85pub type SER = crate::Reg<ser::SER_SPEC>;
86#[doc = "Slave Enable Register: This register enables the individual slave select output lines from the SPI Master. You cannot write to this register when SPI Master is busy."]
87pub mod ser;
88#[doc = "BAUDR register accessor: an alias for `Reg<BAUDR_SPEC>`"]
89pub type BAUDR = crate::Reg<baudr::BAUDR_SPEC>;
90#[doc = "Baud Rate Select Register: This register derives the frequency of the serial clock that regulates the data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing the SSIENR register (0x008)."]
91pub mod baudr;
92#[doc = "TXFTLR register accessor: an alias for `Reg<TXFTLR_SPEC>`"]
93pub type TXFTLR = crate::Reg<txftlr::TXFTLR_SPEC>;
94#[doc = "Transmit FFIFO Threshold Level Register: This register controls the threshold value for the transmit FIFO memory."]
95pub mod txftlr;
96#[doc = "RXFTLR register accessor: an alias for `Reg<RXFTLR_SPEC>`"]
97pub type RXFTLR = crate::Reg<rxftlr::RXFTLR_SPEC>;
98#[doc = "Receive FIFO Threshold Level Register: This register controls the threshold value for the receive FIFO memory."]
99pub mod rxftlr;
100#[doc = "TXFLR register accessor: an alias for `Reg<TXFLR_SPEC>`"]
101pub type TXFLR = crate::Reg<txflr::TXFLR_SPEC>;
102#[doc = "Transmit FIFO Level Register: This register contains the number of valid data entries in the transmit FIFO memory."]
103pub mod txflr;
104#[doc = "RXFLR register accessor: an alias for `Reg<RXFLR_SPEC>`"]
105pub type RXFLR = crate::Reg<rxflr::RXFLR_SPEC>;
106#[doc = "Receive FIFO Level Register: This register contains the number of valid data entries in FIFO memory. This register can be read at any time."]
107pub mod rxflr;
108#[doc = "SR register accessor: an alias for `Reg<SR_SPEC>`"]
109pub type SR = crate::Reg<sr::SR_SPEC>;
110#[doc = "Status Register: This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. This status register may be read at any time. None of the bits in this register request an interrupt."]
111pub mod sr;
112#[doc = "IMR register accessor: an alias for `Reg<IMR_SPEC>`"]
113pub type IMR = crate::Reg<imr::IMR_SPEC>;
114#[doc = "Interrupt Mask Register: This read/write register masks or enables all interrupts generated by the SPI Master."]
115pub mod imr;
116#[doc = "ISR register accessor: an alias for `Reg<ISR_SPEC>`"]
117pub type ISR = crate::Reg<isr::ISR_SPEC>;
118#[doc = "Interrupt Status Register: This register reports the status of SPI Master interrupts after they have been masked."]
119pub mod isr;
120#[doc = "RISR register accessor: an alias for `Reg<RISR_SPEC>`"]
121pub type RISR = crate::Reg<risr::RISR_SPEC>;
122#[doc = "Raw Interrupt Status Register: This read-only register reports the status of the SPI Master interrupts prior to masking."]
123pub mod risr;
124#[doc = "TXOICR register accessor: an alias for `Reg<TXOICR_SPEC>`"]
125pub type TXOICR = crate::Reg<txoicr::TXOICR_SPEC>;
126#[doc = "Transmit FIFO Overflow Interrupt Clear Register."]
127pub mod txoicr;
128#[doc = "RXOICR register accessor: an alias for `Reg<RXOICR_SPEC>`"]
129pub type RXOICR = crate::Reg<rxoicr::RXOICR_SPEC>;
130#[doc = "Receive FIFO Overflow Interrupt Clear Register."]
131pub mod rxoicr;
132#[doc = "RXUICR register accessor: an alias for `Reg<RXUICR_SPEC>`"]
133pub type RXUICR = crate::Reg<rxuicr::RXUICR_SPEC>;
134#[doc = "Receive FIFO Underflow Interrupt Clear Register."]
135pub mod rxuicr;
136#[doc = "MSTICR register accessor: an alias for `Reg<MSTICR_SPEC>`"]
137pub type MSTICR = crate::Reg<msticr::MSTICR_SPEC>;
138#[doc = "Multi-Master Interrupt Clear Register."]
139pub mod msticr;
140#[doc = "ICR register accessor: an alias for `Reg<ICR_SPEC>`"]
141pub type ICR = crate::Reg<icr::ICR_SPEC>;
142#[doc = "Interrupt Clear Register."]
143pub mod icr;
144#[doc = "IDR register accessor: an alias for `Reg<IDR_SPEC>`"]
145pub type IDR = crate::Reg<idr::IDR_SPEC>;
146#[doc = "Identification Code. This register contains the peripherals identification code."]
147pub mod idr;
148#[doc = "SSI_COMP_VERSION register accessor: an alias for `Reg<SSI_COMP_VERSION_SPEC>`"]
149pub type SSI_COMP_VERSION = crate::Reg<ssi_comp_version::SSI_COMP_VERSION_SPEC>;
150#[doc = "Contains the hex representation of the component version. Consists of ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01*."]
151pub mod ssi_comp_version;
152#[doc = "DR0 register accessor: an alias for `Reg<DR0_SPEC>`"]
153pub type DR0 = crate::Reg<dr0::DR0_SPEC>;
154#[doc = "The SPI Master data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. Please refer to SSIENR register (0x008) to enable and disable the SPI Master. The DR register in the SPI Master occupies 131(for TX)/8(for RX) 32-bit address locations of the memory map to facilitate AHB burst transfers. Writing to any of these address locations has the same effect as pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI Master are not addressable."]
155pub mod dr0;