Module spi 

SPI peripheral control

Modules

baudr

Baud Rate Select Register: This register derives the frequency of the serial clock that regulates the data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing the SSIENR register (0x008).

ctrlr0

Control Register 0: This register controls the serial data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008).

ctrlr1

Control Register 1: CTRLR1 register controls the end of serial transfers when in receive-only mode. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008).

dr0

The SPI Master data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. Please refer to SSIENR register (0x008) to enable and disable the SPI Master. The DR register in the SPI Master occupies 131(for TX)/8(for RX) 32-bit address locations of the memory map to facilitate AHB burst transfers. Writing to any of these address locations has the same effect as pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI Master are not addressable.

icr

Interrupt Clear Register.

idr

Identification Code. This register contains the peripherals identification code.

imr

Interrupt Mask Register: This read/write register masks or enables all interrupts generated by the SPI Master.

isr

Interrupt Status Register: This register reports the status of SPI Master interrupts after they have been masked.

msticr

Multi-Master Interrupt Clear Register.

risr

Raw Interrupt Status Register: This read-only register reports the status of the SPI Master interrupts prior to masking.

rxflr

Receive FIFO Level Register: This register contains the number of valid data entries in FIFO memory. This register can be read at any time.

rxftlr

Receive FIFO Threshold Level Register: This register controls the threshold value for the receive FIFO memory.

rxoicr

Receive FIFO Overflow Interrupt Clear Register.

rxuicr

Receive FIFO Underflow Interrupt Clear Register.

ser

Slave Enable Register: This register enables the individual slave select output lines from the SPI Master. You cannot write to this register when SPI Master is busy.

sr

Status Register: This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. This status register may be read at any time. None of the bits in this register request an interrupt.

ssi_comp_version

Contains the hex representation of the component version. Consists of ASCII value for each number in the version, followed by . For example 32_30_31_2A represents the version 2.01.

ssienr

SSI Enable Register: This register enables and disables the SPI Master. The following SPI Master registers are NOT writeable when SPI Master is enabled =1: CTRLR0, CTRLR1, BAUDR. You must set SSIENR = 0, before writing these 3 registers. The following SPI Master registers are writeable ONLY when the SPI Master is enabled = 1: DR0.

txflr

Transmit FIFO Level Register: This register contains the number of valid data entries in the transmit FIFO memory.

txftlr

Transmit FFIFO Threshold Level Register: This register controls the threshold value for the transmit FIFO memory.

txoicr

Transmit FIFO Overflow Interrupt Clear Register.

Structs

RegisterBlock

Register block

Type Aliases

BAUDR

BAUDR register accessor: an alias for Reg<BAUDR_SPEC>

CTRLR0

CTRLR0 register accessor: an alias for Reg<CTRLR0_SPEC>

CTRLR1

CTRLR1 register accessor: an alias for Reg<CTRLR1_SPEC>

DR0

DR0 register accessor: an alias for Reg<DR0_SPEC>

ICR

ICR register accessor: an alias for Reg<ICR_SPEC>

IDR

IDR register accessor: an alias for Reg<IDR_SPEC>

IMR

IMR register accessor: an alias for Reg<IMR_SPEC>

ISR

ISR register accessor: an alias for Reg<ISR_SPEC>

MSTICR

MSTICR register accessor: an alias for Reg<MSTICR_SPEC>

RISR

RISR register accessor: an alias for Reg<RISR_SPEC>

RXFLR

RXFLR register accessor: an alias for Reg<RXFLR_SPEC>

RXFTLR

RXFTLR register accessor: an alias for Reg<RXFTLR_SPEC>

RXOICR

RXOICR register accessor: an alias for Reg<RXOICR_SPEC>

RXUICR

RXUICR register accessor: an alias for Reg<RXUICR_SPEC>

SER

SER register accessor: an alias for Reg<SER_SPEC>

SR

SR register accessor: an alias for Reg<SR_SPEC>

SSIENR

SSIENR register accessor: an alias for Reg<SSIENR_SPEC>

SSI_COMP_VERSION

SSI_COMP_VERSION register accessor: an alias for Reg<SSI_COMP_VERSION_SPEC>

TXFLR

TXFLR register accessor: an alias for Reg<TXFLR_SPEC>

TXFTLR

TXFTLR register accessor: an alias for Reg<TXFTLR_SPEC>

TXOICR

TXOICR register accessor: an alias for Reg<TXOICR_SPEC>