#[doc = "Reader of register CCUCLKCR"]
pub type R = crate::R<u32, super::CCUCLKCR>;
#[doc = "Writer for register CCUCLKCR"]
pub type W = crate::W<u32, super::CCUCLKCR>;
#[doc = "Register CCUCLKCR `reset()`'s with value 0"]
impl crate::ResetValue for super::CCUCLKCR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "CCU Clock Divider Enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCUDIV_A {
#[doc = "0: fCCU = fSYS"]
VALUE1 = 0,
#[doc = "1: fCCU = fSYS / 2"]
VALUE2 = 1,
}
impl From<CCUDIV_A> for bool {
#[inline(always)]
fn from(variant: CCUDIV_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `CCUDIV`"]
pub type CCUDIV_R = crate::R<bool, CCUDIV_A>;
impl CCUDIV_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CCUDIV_A {
match self.bits {
false => CCUDIV_A::VALUE1,
true => CCUDIV_A::VALUE2,
}
}
#[doc = "Checks if the value of the field is `VALUE1`"]
#[inline(always)]
pub fn is_value1(&self) -> bool {
*self == CCUDIV_A::VALUE1
}
#[doc = "Checks if the value of the field is `VALUE2`"]
#[inline(always)]
pub fn is_value2(&self) -> bool {
*self == CCUDIV_A::VALUE2
}
}
#[doc = "Write proxy for field `CCUDIV`"]
pub struct CCUDIV_W<'a> {
w: &'a mut W,
}
impl<'a> CCUDIV_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CCUDIV_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "fCCU = fSYS"]
#[inline(always)]
pub fn value1(self) -> &'a mut W {
self.variant(CCUDIV_A::VALUE1)
}
#[doc = "fCCU = fSYS / 2"]
#[inline(always)]
pub fn value2(self) -> &'a mut W {
self.variant(CCUDIV_A::VALUE2)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
impl R {
#[doc = "Bit 0 - CCU Clock Divider Enable"]
#[inline(always)]
pub fn ccudiv(&self) -> CCUDIV_R {
CCUDIV_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - CCU Clock Divider Enable"]
#[inline(always)]
pub fn ccudiv(&mut self) -> CCUDIV_W {
CCUDIV_W { w: self }
}
}