vyre 0.4.0

GPU compute intermediate representation with a standard operation library
Documentation 
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use crate::ir::{Expr, Program};
use crate::ops::primitive;
use crate::ops::{AlgebraicLaw, OpSpec, F32_INPUTS, F32_OUTPUTS};

// Element-wise negation of an f32 buffer.


pub const LAWS: &[AlgebraicLaw] = &[AlgebraicLaw::Involution];

/// f32 element-wise negation operation.
#[derive(Debug, Clone, Copy, Default)]
pub struct F32Neg;

impl F32Neg {
    /// Declarative operation specification.
    ///
    /// Laws are declared as explicit `AlgebraicLaw` values on `SPEC`.
    pub const SPEC: OpSpec = OpSpec::composition_inlinable(
        "primitive.float.f32_neg",
        F32_INPUTS,
        F32_OUTPUTS,
        LAWS,
        Self::program,
    );

    /// Build the canonical IR program.
    ///
    /// # Examples
    ///
    /// ```
    /// use vyre::ir::Expr;
    /// use vyre::ops::primitive::float::f32_neg::F32Neg;
    ///
    /// let _expr = Expr::negate(Expr::f32(3.14));
    /// let program = F32Neg::program();
    /// assert!(!program.entry().is_empty());
    /// ```
    #[must_use]
    pub fn program() -> Program {
        primitive::unary_f32_program(Expr::negate)
    }
}

// WGSL lowering marker for `primitive.float.f32_neg`.
//
// Not a stub: this is a zero-overhead Category A marker. `F32Neg::program`
// builds concrete IR through `core/src/ops/primitive/unary_f32_program.rs`;
// `core/src/lower/wgsl/expr.rs::emit_unop` emits WGSL.
// `core/tests/conformance.rs::conformance_all_primitives` verifies
// lowered GPU bytes are bit-exact against the conform CPU reference.
//
// ```wgsl
// _vyre_store_out(idx, (-_vyre_load_a(idx)));
// ```