vyre 0.4.0

GPU compute intermediate representation with a standard operation library
Documentation 
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use crate::ir::{Expr, Program};
use crate::ops::primitive;
use crate::ops::{AlgebraicLaw, OpSpec, F32_F32_INPUTS, F32_OUTPUTS};

// Element-wise division of two f32 buffers.


// `LeftAbsorbing { element: 0 }` fails on `0 / 0 = NaN` (and more
// subtly on `0 / Inf = 0` which only holds for positive zero). The
// `InverseOf { f32_mul }` claim fails on subnormals (rounding) and on
// any NaN payload. Per audit `primitive-laws-kimi-AUDIT`, F32Div
// satisfies only right-identity-by-one.
pub const LAWS: &[AlgebraicLaw] =
    &[AlgebraicLaw::RightIdentity { element: 1.0f32.to_bits() }];

/// f32 element-wise division operation.
#[derive(Debug, Clone, Copy, Default)]
pub struct F32Div;

impl F32Div {
    /// Declarative operation specification.
    pub const SPEC: OpSpec = OpSpec::composition_inlinable(
        "primitive.float.f32_div",
        F32_F32_INPUTS,
        F32_OUTPUTS,
        LAWS,
        Self::program,
    );

    /// Build the canonical IR program.
    ///
    /// # Examples
    ///
    /// ```
    /// use vyre::ir::Expr;
    /// use vyre::ops::primitive::float::f32_div::F32Div;
    ///
    /// let program = F32Div::program();
    /// assert!(!program.entry().is_empty());
    /// ```
    #[must_use]
    pub fn program() -> Program {
        primitive::binary_f32_program(Expr::div)
    }
}

// WGSL lowering marker for `primitive.float.f32_div`.
//
// Not a stub: this is a zero-overhead Category A marker. `F32Div::program`
// builds concrete IR through `core/src/ops/primitive/binary_f32_program.rs`;
// `core/src/lower/wgsl/expr.rs::emit_binop` emits WGSL.
// `core/tests/conformance.rs::conformance_all_primitives` verifies
// lowered GPU bytes are bit-exact against the conform CPU reference.
//
// ```wgsl
// _vyre_store_out(idx, (_vyre_load_a(idx) / _vyre_load_b(idx)));
// ```