stm32mp1 0.16.0

Device support crates for STM32MP1 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181

///Register `DCTRL` reader
pub type R = crate::R<DCTRLrs>;
///Register `DCTRL` writer
pub type W = crate::W<DCTRLrs>;
///Field `DTEN` reader - DTEN
pub type DTEN_R = crate::BitReader;
///Field `DTEN` writer - DTEN
pub type DTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DTDIR` reader - DTDIR
pub type DTDIR_R = crate::BitReader;
///Field `DTDIR` writer - DTDIR
pub type DTDIR_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DTMODE` reader - DTMODE
pub type DTMODE_R = crate::FieldReader;
///Field `DTMODE` writer - DTMODE
pub type DTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `DBLOCKSIZE` reader - DBLOCKSIZE
pub type DBLOCKSIZE_R = crate::FieldReader;
///Field `DBLOCKSIZE` writer - DBLOCKSIZE
pub type DBLOCKSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
///Field `RWSTART` reader - RWSTART
pub type RWSTART_R = crate::BitReader;
///Field `RWSTART` writer - RWSTART
pub type RWSTART_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RWSTOP` reader - RWSTOP
pub type RWSTOP_R = crate::BitReader;
///Field `RWSTOP` writer - RWSTOP
pub type RWSTOP_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RWMOD` reader - RWMOD
pub type RWMOD_R = crate::BitReader;
///Field `RWMOD` writer - RWMOD
pub type RWMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SDIOEN` reader - SDIOEN
pub type SDIOEN_R = crate::BitReader;
///Field `SDIOEN` writer - SDIOEN
pub type SDIOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `BOOTACKEN` reader - BOOTACKEN
pub type BOOTACKEN_R = crate::BitReader;
///Field `BOOTACKEN` writer - BOOTACKEN
pub type BOOTACKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FIFORST` reader - FIFORST
pub type FIFORST_R = crate::BitReader;
///Field `FIFORST` writer - FIFORST
pub type FIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - DTEN
    #[inline(always)]
    pub fn dten(&self) -> DTEN_R {
        DTEN_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - DTDIR
    #[inline(always)]
    pub fn dtdir(&self) -> DTDIR_R {
        DTDIR_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bits 2:3 - DTMODE
    #[inline(always)]
    pub fn dtmode(&self) -> DTMODE_R {
        DTMODE_R::new(((self.bits >> 2) & 3) as u8)
    }
    ///Bits 4:7 - DBLOCKSIZE
    #[inline(always)]
    pub fn dblocksize(&self) -> DBLOCKSIZE_R {
        DBLOCKSIZE_R::new(((self.bits >> 4) & 0x0f) as u8)
    }
    ///Bit 8 - RWSTART
    #[inline(always)]
    pub fn rwstart(&self) -> RWSTART_R {
        RWSTART_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - RWSTOP
    #[inline(always)]
    pub fn rwstop(&self) -> RWSTOP_R {
        RWSTOP_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - RWMOD
    #[inline(always)]
    pub fn rwmod(&self) -> RWMOD_R {
        RWMOD_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - SDIOEN
    #[inline(always)]
    pub fn sdioen(&self) -> SDIOEN_R {
        SDIOEN_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - BOOTACKEN
    #[inline(always)]
    pub fn bootacken(&self) -> BOOTACKEN_R {
        BOOTACKEN_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - FIFORST
    #[inline(always)]
    pub fn fiforst(&self) -> FIFORST_R {
        FIFORST_R::new(((self.bits >> 13) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DCTRL")
            .field("dten", &self.dten())
            .field("dtdir", &self.dtdir())
            .field("dtmode", &self.dtmode())
            .field("dblocksize", &self.dblocksize())
            .field("rwstart", &self.rwstart())
            .field("rwstop", &self.rwstop())
            .field("rwmod", &self.rwmod())
            .field("sdioen", &self.sdioen())
            .field("bootacken", &self.bootacken())
            .field("fiforst", &self.fiforst())
            .finish()
    }
}
impl W {
    ///Bit 0 - DTEN
    #[inline(always)]
    pub fn dten(&mut self) -> DTEN_W<DCTRLrs> {
        DTEN_W::new(self, 0)
    }
    ///Bit 1 - DTDIR
    #[inline(always)]
    pub fn dtdir(&mut self) -> DTDIR_W<DCTRLrs> {
        DTDIR_W::new(self, 1)
    }
    ///Bits 2:3 - DTMODE
    #[inline(always)]
    pub fn dtmode(&mut self) -> DTMODE_W<DCTRLrs> {
        DTMODE_W::new(self, 2)
    }
    ///Bits 4:7 - DBLOCKSIZE
    #[inline(always)]
    pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<DCTRLrs> {
        DBLOCKSIZE_W::new(self, 4)
    }
    ///Bit 8 - RWSTART
    #[inline(always)]
    pub fn rwstart(&mut self) -> RWSTART_W<DCTRLrs> {
        RWSTART_W::new(self, 8)
    }
    ///Bit 9 - RWSTOP
    #[inline(always)]
    pub fn rwstop(&mut self) -> RWSTOP_W<DCTRLrs> {
        RWSTOP_W::new(self, 9)
    }
    ///Bit 10 - RWMOD
    #[inline(always)]
    pub fn rwmod(&mut self) -> RWMOD_W<DCTRLrs> {
        RWMOD_W::new(self, 10)
    }
    ///Bit 11 - SDIOEN
    #[inline(always)]
    pub fn sdioen(&mut self) -> SDIOEN_W<DCTRLrs> {
        SDIOEN_W::new(self, 11)
    }
    ///Bit 12 - BOOTACKEN
    #[inline(always)]
    pub fn bootacken(&mut self) -> BOOTACKEN_W<DCTRLrs> {
        BOOTACKEN_W::new(self, 12)
    }
    ///Bit 13 - FIFORST
    #[inline(always)]
    pub fn fiforst(&mut self) -> FIFORST_W<DCTRLrs> {
        FIFORST_W::new(self, 13)
    }
}
/**The SDMMC_DCTRL register control the data path state machine (DPSM).

You can [`read`](crate::Reg::read) this register and get [`dctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP153.html#SDMMC1:DCTRL)*/
pub struct DCTRLrs;
impl crate::RegisterSpec for DCTRLrs {
    type Ux = u32;
}
///`read()` method returns [`dctrl::R`](R) reader structure
impl crate::Readable for DCTRLrs {}
///`write(|w| ..)` method takes [`dctrl::W`](W) writer structure
impl crate::Writable for DCTRLrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets DCTRL to value 0
impl crate::Resettable for DCTRLrs {}