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///Register `ICR` writer
pub type W = crate::W<ICRrs>;
///Field `SEIF` writer - SEIF
pub type SEIF_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `XONEIF` writer - Execute-only execute-Never Error Interrupt Flag clear
pub type XONEIF_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `KEIF` writer - KEIF
pub type KEIF_W<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
///Bit 0 - SEIF
#[inline(always)]
pub fn seif(&mut self) -> SEIF_W<ICRrs> {
SEIF_W::new(self, 0)
}
///Bit 1 - Execute-only execute-Never Error Interrupt Flag clear
#[inline(always)]
pub fn xoneif(&mut self) -> XONEIF_W<ICRrs> {
XONEIF_W::new(self, 1)
}
///Bit 2 - KEIF
#[inline(always)]
pub fn keif(&mut self) -> KEIF_W<ICRrs> {
KEIF_W::new(self, 2)
}
}
/**OTFDEC interrupt clear register
You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L562.html#OTFDEC1:ICR)*/
pub struct ICRrs;
impl crate::RegisterSpec for ICRrs {
type Ux = u32;
}
///`write(|w| ..)` method takes [`icr::W`](W) writer structure
impl crate::Writable for ICRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets ICR to value 0
impl crate::Resettable for ICRrs {}