stm32l5 0.16.0

/*!Peripheral access API for STM32L552 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 3;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG();
    fn PVD_PVM();
    fn RTC();
    fn RTC_S();
    fn TAMP();
    fn TAMP_S();
    fn FLASH();
    fn FLASH_S();
    fn GTZC();
    fn RCC();
    fn RCC_S();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn EXTI5();
    fn EXTI6();
    fn EXTI7();
    fn EXTI8();
    fn EXTI9();
    fn EXTI10();
    fn EXTI11();
    fn EXTI12();
    fn EXTI13();
    fn EXTI14();
    fn EXTI15();
    fn DMAMUX1_OVR();
    fn DMAMUX1_OVR_S();
    fn DMA1_CH1();
    fn DMA1_CH2();
    fn DMA1_CH3();
    fn DMA1_CH4();
    fn DMA1_CH5();
    fn DMA1_CH6();
    fn DMA1_CH7();
    fn DMA1_CHANNEL8();
    fn ADC1_2();
    fn DAC();
    fn FDCAN1_IT0();
    fn FDCAN1_IT1();
    fn TIM1_BRK();
    fn TIM1_UP();
    fn TIM1_TRG_COM();
    fn TIM1_CC();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn TIM5();
    fn TIM6();
    fn TIM7();
    fn TIM8_BRK();
    fn TIM8_UP();
    fn TIM8_TRG_COM();
    fn TIM8_CC();
    fn I2C1_EV();
    fn I2C1_ER();
    fn I2C2_EV();
    fn I2C2_ER();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn USART2();
    fn USART3();
    fn UART4();
    fn UART5();
    fn LPUART1();
    fn LPTIM1();
    fn LPTIM2();
    fn TIM15();
    fn TIM16();
    fn TIM17();
    fn COMP();
    fn USB_FS();
    fn CRS();
    fn FMC();
    fn OCTOSPI1();
    fn SDMMC1();
    fn DMA2_CH1();
    fn DMA2_CH2();
    fn DMA2_CH3();
    fn DMA2_CH4();
    fn DMA2_CH5();
    fn DMA2_CH6();
    fn DMA2_CH7();
    fn DMA2_CH8();
    fn I2C3_EV();
    fn I2C3_ER();
    fn SAI1();
    fn SAI2();
    fn TSC();
    fn RNG();
    fn HASH();
    fn LPTIM3();
    fn SPI3();
    fn I2C4_ER();
    fn I2C4_EV();
    fn DFSDM1_FLT0();
    fn DFSDM1_FLT1();
    fn DFSDM1_FLT2();
    fn DFSDM1_FLT3();
    fn UCPD1();
    fn ICACHE();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 108] = [
    Vector { _handler: WWDG },
    Vector { _handler: PVD_PVM },
    Vector { _handler: RTC },
    Vector { _handler: RTC_S },
    Vector { _handler: TAMP },
    Vector { _handler: TAMP_S },
    Vector { _handler: FLASH },
    Vector { _handler: FLASH_S },
    Vector { _handler: GTZC },
    Vector { _handler: RCC },
    Vector { _handler: RCC_S },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector { _handler: EXTI5 },
    Vector { _handler: EXTI6 },
    Vector { _handler: EXTI7 },
    Vector { _handler: EXTI8 },
    Vector { _handler: EXTI9 },
    Vector { _handler: EXTI10 },
    Vector { _handler: EXTI11 },
    Vector { _handler: EXTI12 },
    Vector { _handler: EXTI13 },
    Vector { _handler: EXTI14 },
    Vector { _handler: EXTI15 },
    Vector {
        _handler: DMAMUX1_OVR,
    },
    Vector {
        _handler: DMAMUX1_OVR_S,
    },
    Vector { _handler: DMA1_CH1 },
    Vector { _handler: DMA1_CH2 },
    Vector { _handler: DMA1_CH3 },
    Vector { _handler: DMA1_CH4 },
    Vector { _handler: DMA1_CH5 },
    Vector { _handler: DMA1_CH6 },
    Vector { _handler: DMA1_CH7 },
    Vector {
        _handler: DMA1_CHANNEL8,
    },
    Vector { _handler: ADC1_2 },
    Vector { _handler: DAC },
    Vector {
        _handler: FDCAN1_IT0,
    },
    Vector {
        _handler: FDCAN1_IT1,
    },
    Vector { _handler: TIM1_BRK },
    Vector { _handler: TIM1_UP },
    Vector {
        _handler: TIM1_TRG_COM,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector { _handler: TIM5 },
    Vector { _handler: TIM6 },
    Vector { _handler: TIM7 },
    Vector { _handler: TIM8_BRK },
    Vector { _handler: TIM8_UP },
    Vector {
        _handler: TIM8_TRG_COM,
    },
    Vector { _handler: TIM8_CC },
    Vector { _handler: I2C1_EV },
    Vector { _handler: I2C1_ER },
    Vector { _handler: I2C2_EV },
    Vector { _handler: I2C2_ER },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: USART2 },
    Vector { _handler: USART3 },
    Vector { _handler: UART4 },
    Vector { _handler: UART5 },
    Vector { _handler: LPUART1 },
    Vector { _handler: LPTIM1 },
    Vector { _handler: LPTIM2 },
    Vector { _handler: TIM15 },
    Vector { _handler: TIM16 },
    Vector { _handler: TIM17 },
    Vector { _handler: COMP },
    Vector { _handler: USB_FS },
    Vector { _handler: CRS },
    Vector { _handler: FMC },
    Vector { _handler: OCTOSPI1 },
    Vector { _reserved: 0 },
    Vector { _handler: SDMMC1 },
    Vector { _reserved: 0 },
    Vector { _handler: DMA2_CH1 },
    Vector { _handler: DMA2_CH2 },
    Vector { _handler: DMA2_CH3 },
    Vector { _handler: DMA2_CH4 },
    Vector { _handler: DMA2_CH5 },
    Vector { _handler: DMA2_CH6 },
    Vector { _handler: DMA2_CH7 },
    Vector { _handler: DMA2_CH8 },
    Vector { _handler: I2C3_EV },
    Vector { _handler: I2C3_ER },
    Vector { _handler: SAI1 },
    Vector { _handler: SAI2 },
    Vector { _handler: TSC },
    Vector { _reserved: 0 },
    Vector { _handler: RNG },
    Vector { _reserved: 0 },
    Vector { _handler: HASH },
    Vector { _reserved: 0 },
    Vector { _handler: LPTIM3 },
    Vector { _handler: SPI3 },
    Vector { _handler: I2C4_ER },
    Vector { _handler: I2C4_EV },
    Vector {
        _handler: DFSDM1_FLT0,
    },
    Vector {
        _handler: DFSDM1_FLT1,
    },
    Vector {
        _handler: DFSDM1_FLT2,
    },
    Vector {
        _handler: DFSDM1_FLT3,
    },
    Vector { _handler: UCPD1 },
    Vector { _handler: ICACHE },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG = 0,
    ///1 - PVD/PVM1/PVM2/PVM3/PVM4 through EXTI
    PVD_PVM = 1,
    ///2 - RTC global interrupts (EXTI line 17)
    RTC = 2,
    ///3 - RTC secure global interrupts (EXTI line 18)
    RTC_S = 3,
    ///4 - TAMPTamper global interrupt (EXTI line 19)
    TAMP = 4,
    ///5 - Tamper secure global interrupt (EXTI line 20)
    TAMP_S = 5,
    ///6 - Flash global interrupt
    FLASH = 6,
    ///7 - Flash memory secure global interrupt
    FLASH_S = 7,
    ///8 - TZIC secure global interrupt
    GTZC = 8,
    ///9 - RCC global interrupt
    RCC = 9,
    ///10 - RCC SECURE GLOBAL INTERRUPT
    RCC_S = 10,
    ///11 - EXTI line0 interrupt
    EXTI0 = 11,
    ///12 - EXTI line1 interrupt
    EXTI1 = 12,
    ///13 - EXTI line2 interrupt
    EXTI2 = 13,
    ///14 - EXTI line3 interrupt
    EXTI3 = 14,
    ///15 - EXTI line4 interrupt
    EXTI4 = 15,
    ///16 - EXTI line5 interrupt
    EXTI5 = 16,
    ///17 - EXTI line6 interrupt
    EXTI6 = 17,
    ///18 - EXTI line7 interrupt
    EXTI7 = 18,
    ///19 - EXTI line8 interrupt
    EXTI8 = 19,
    ///20 - EXTI line9 interrupt
    EXTI9 = 20,
    ///21 - EXTI line10 interrupt
    EXTI10 = 21,
    ///22 - EXTI line11 interrupt
    EXTI11 = 22,
    ///23 - EXTI line12 interrupt
    EXTI12 = 23,
    ///24 - EXTI line13 interrupt
    EXTI13 = 24,
    ///25 - EXTI line14 interrupt
    EXTI14 = 25,
    ///26 - EXTI line15 interrupt
    EXTI15 = 26,
    ///27 - DMAMUX overrun interrupt
    DMAMUX1_OVR = 27,
    ///28 - DMAMUX1 secure overRun interrupt
    DMAMUX1_OVR_S = 28,
    ///29 - DMA1 Channel1 global interrupt
    DMA1_CH1 = 29,
    ///30 - DMA1 Channel2 global interrupt
    DMA1_CH2 = 30,
    ///31 - DMA1 Channel3 interrupt
    DMA1_CH3 = 31,
    ///32 - DMA1 Channel4 interrupt
    DMA1_CH4 = 32,
    ///33 - DMA1 Channel5 interrupt
    DMA1_CH5 = 33,
    ///34 - DMA1 Channel6 interrupt
    DMA1_CH6 = 34,
    ///35 - DMA1 Channel 7 interrupt
    DMA1_CH7 = 35,
    ///36 - DMA1_Channel8
    DMA1_CHANNEL8 = 36,
    ///37 - ADC1_2 global interrupt
    ADC1_2 = 37,
    ///38 - DAC global interrupt
    DAC = 38,
    ///39 - FDCAN1 Interrupt 0
    FDCAN1_IT0 = 39,
    ///40 - FDCAN1 Interrupt 1
    FDCAN1_IT1 = 40,
    ///41 - TIM1 Break
    TIM1_BRK = 41,
    ///42 - TIM1 Update
    TIM1_UP = 42,
    ///43 - TIM1 Trigger and Commutation
    TIM1_TRG_COM = 43,
    ///44 - TIM1 Capture Compare interrupt
    TIM1_CC = 44,
    ///45 - TIM2 global interrupt
    TIM2 = 45,
    ///46 - TIM3 global interrupt
    TIM3 = 46,
    ///47 - TIM4 global interrupt
    TIM4 = 47,
    ///48 - TIM5 global interrupt
    TIM5 = 48,
    ///49 - TIM6 global interrupt
    TIM6 = 49,
    ///50 - TIM7 global interrupt
    TIM7 = 50,
    ///51 - TIM8 Break Interrupt
    TIM8_BRK = 51,
    ///52 - TIM8 Update Interrupt
    TIM8_UP = 52,
    ///53 - TIM8 Trigger and Commutation Interrupt
    TIM8_TRG_COM = 53,
    ///54 - TIM8 Capture Compare Interrupt
    TIM8_CC = 54,
    ///55 - I2C1 event interrupt
    I2C1_EV = 55,
    ///56 - I2C1 error interrupt
    I2C1_ER = 56,
    ///57 - I2C2 event interrupt
    I2C2_EV = 57,
    ///58 - I2C2 error interrupt
    I2C2_ER = 58,
    ///59 - SPI1 global interrupt
    SPI1 = 59,
    ///60 - SPI2 global interrupt
    SPI2 = 60,
    ///61 - USART1 global interrupt
    USART1 = 61,
    ///62 - USART2 global interrupt
    USART2 = 62,
    ///63 - USART3 global interrupt
    USART3 = 63,
    ///64 - UART4 global interrupt
    UART4 = 64,
    ///65 - UART5 global interrupt
    UART5 = 65,
    ///66 - LPUART1 global interrupt
    LPUART1 = 66,
    ///67 - LP TIM1 interrupt
    LPTIM1 = 67,
    ///68 - LP TIM2 interrupt
    LPTIM2 = 68,
    ///69 - TIM15 global interrupt
    TIM15 = 69,
    ///70 - TIM16 global interrupt
    TIM16 = 70,
    ///71 - TIM17 global interrupt
    TIM17 = 71,
    ///72 - COMP1 and COMP2 interrupts
    COMP = 72,
    ///73 - USB FS global interrupt
    USB_FS = 73,
    ///74 - Clock recovery system global interrupt
    CRS = 74,
    ///75 - FMC global interrupt
    FMC = 75,
    ///76 - OCTOSPI1 global interrupt
    OCTOSPI1 = 76,
    ///78 - SDMMC1 global interrupt
    SDMMC1 = 78,
    ///80 - DMA2_CH1
    DMA2_CH1 = 80,
    ///81 - DMA2_CH2
    DMA2_CH2 = 81,
    ///82 - DMA2_CH3
    DMA2_CH3 = 82,
    ///83 - DMA2_CH4
    DMA2_CH4 = 83,
    ///84 - DMA2_CH5
    DMA2_CH5 = 84,
    ///85 - DMA2_CH6
    DMA2_CH6 = 85,
    ///86 - DMA2_CH7
    DMA2_CH7 = 86,
    ///87 - DMA2_CH8
    DMA2_CH8 = 87,
    ///88 - I2C3 event interrupt
    I2C3_EV = 88,
    ///89 - I2C3 error interrupt
    I2C3_ER = 89,
    ///90 - SAI1 global interrupt
    SAI1 = 90,
    ///91 - SAI2 global interrupt
    SAI2 = 91,
    ///92 - TSC global interrupt
    TSC = 92,
    ///94 - RNG global interrupt
    RNG = 94,
    ///96 - HASH interrupt
    HASH = 96,
    ///98 - LPTIM3
    LPTIM3 = 98,
    ///99 - SPI3
    SPI3 = 99,
    ///100 - I2C4 error interrupt
    I2C4_ER = 100,
    ///101 - I2C4 event interrupt
    I2C4_EV = 101,
    ///102 - DFSDM1_FLT0 global interrupt
    DFSDM1_FLT0 = 102,
    ///103 - DFSDM1_FLT1 global interrupt
    DFSDM1_FLT1 = 103,
    ///104 - DFSDM1_FLT2 global interrupt
    DFSDM1_FLT2 = 104,
    ///105 - DFSDM1_FLT3 global interrupt
    DFSDM1_FLT3 = 105,
    ///106 - UCPD global interrupt
    UCPD1 = 106,
    ///107 - ICACHE
    ICACHE = 107,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC1)
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4202_8000>;
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc1;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC1)
pub type SEC_ADC1 = crate::Periph<adc1::RegisterBlock, 0x5202_8000>;
impl core::fmt::Debug for SEC_ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_ADC1").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as sec_adc1;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC1)
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x4202_8100>;
impl core::fmt::Debug for ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC2").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC1)
pub type SEC_ADC2 = crate::Periph<adc1::RegisterBlock, 0x5202_8100>;
impl core::fmt::Debug for SEC_ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_ADC2").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as sec_adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC_Common)
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4202_8300>;
impl core::fmt::Debug for ADC_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc_common;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ADC_Common)
pub type SEC_ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x5202_8300>;
impl core::fmt::Debug for SEC_ADC_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_ADC_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc_common as sec_adc_common;
///Comparator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#COMP)
pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0200>;
impl core::fmt::Debug for COMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("COMP").finish()
    }
}
///Comparator
pub mod comp;
///Comparator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#COMP)
pub type SEC_COMP = crate::Periph<comp::RegisterBlock, 0x5001_0200>;
impl core::fmt::Debug for SEC_COMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_COMP").finish()
    }
}
///Comparator
pub use self::comp as sec_comp;
///Cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#CRC)
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
///Cyclic redundancy check calculation unit
pub mod crc;
///Cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#CRC)
pub type SEC_CRC = crate::Periph<crc::RegisterBlock, 0x5002_3000>;
impl core::fmt::Debug for SEC_CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_CRC").finish()
    }
}
///Cyclic redundancy check calculation unit
pub use self::crc as sec_crc;
///Clock recovery system
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#CRS)
pub type CRS = crate::Periph<crs::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for CRS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRS").finish()
    }
}
///Clock recovery system
pub mod crs;
///Clock recovery system
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#CRS)
pub type SEC_CRS = crate::Periph<crs::RegisterBlock, 0x5000_6000>;
impl core::fmt::Debug for SEC_CRS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_CRS").finish()
    }
}
///Clock recovery system
pub use self::crs as sec_crs;
///DAC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DAC)
pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC").finish()
    }
}
///DAC
pub mod dac;
///DAC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DAC)
pub type SEC_DAC = crate::Periph<dac::RegisterBlock, 0x5000_7400>;
impl core::fmt::Debug for SEC_DAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_DAC").finish()
    }
}
///DAC
pub use self::dac as sec_dac;
///MCU debug component
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DBGMCU)
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_4000>;
impl core::fmt::Debug for DBGMCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DBGMCU").finish()
    }
}
///MCU debug component
pub mod dbgmcu;
///Digital filter for sigma delta modulators
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DFSDM1)
pub type DFSDM1 = crate::Periph<dfsdm1::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for DFSDM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DFSDM1").finish()
    }
}
///Digital filter for sigma delta modulators
pub mod dfsdm1;
///Digital filter for sigma delta modulators
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DFSDM1)
pub type SEC_DFSDM1 = crate::Periph<dfsdm1::RegisterBlock, 0x5001_6000>;
impl core::fmt::Debug for SEC_DFSDM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_DFSDM1").finish()
    }
}
///Digital filter for sigma delta modulators
pub use self::dfsdm1 as sec_dfsdm1;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///Direct memory access controller
pub mod dma1;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMA1)
pub type SEC_DMA1 = crate::Periph<dma1::RegisterBlock, 0x5002_0000>;
impl core::fmt::Debug for SEC_DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_DMA1").finish()
    }
}
///Direct memory access controller
pub use self::dma1 as sec_dma1;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///Direct memory access controller
pub use self::dma1 as dma2;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMA1)
pub type SEC_DMA2 = crate::Periph<dma1::RegisterBlock, 0x5002_0400>;
impl core::fmt::Debug for SEC_DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_DMA2").finish()
    }
}
///Direct memory access controller
pub use self::dma1 as sec_dma2;
///Direct memory access Multiplexer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMAMUX1)
pub type DMAMUX1 = crate::Periph<dmamux1::RegisterBlock, 0x4002_0800>;
impl core::fmt::Debug for DMAMUX1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMAMUX1").finish()
    }
}
///Direct memory access Multiplexer
pub mod dmamux1;
///Direct memory access Multiplexer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#DMAMUX1)
pub type SEC_DMAMUX1 = crate::Periph<dmamux1::RegisterBlock, 0x5002_0800>;
impl core::fmt::Debug for SEC_DMAMUX1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_DMAMUX1").finish()
    }
}
///Direct memory access Multiplexer
pub use self::dmamux1 as sec_dmamux1;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4002_f400>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///External interrupt/event controller
pub mod exti;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#EXTI)
pub type SEC_EXTI = crate::Periph<exti::RegisterBlock, 0x5002_f400>;
impl core::fmt::Debug for SEC_EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_EXTI").finish()
    }
}
///External interrupt/event controller
pub use self::exti as sec_exti;
///FDCAN1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FDCAN1)
pub type FDCAN1 = crate::Periph<fdcan1::RegisterBlock, 0x4000_a400>;
impl core::fmt::Debug for FDCAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN1").finish()
    }
}
///FDCAN1
pub mod fdcan1;
///FDCAN1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FDCAN1)
pub type SEC_FDCAN1 = crate::Periph<fdcan1::RegisterBlock, 0x5000_a400>;
impl core::fmt::Debug for SEC_FDCAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_FDCAN1").finish()
    }
}
///FDCAN1
pub use self::fdcan1 as sec_fdcan1;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FLASH)
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FLASH").finish()
    }
}
///Flash
pub mod flash;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FLASH)
pub type SEC_FLASH = crate::Periph<flash::RegisterBlock, 0x5002_2000>;
impl core::fmt::Debug for SEC_FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_FLASH").finish()
    }
}
///Flash
pub use self::flash as sec_flash;
///FMC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC)
pub type FMC = crate::Periph<fmc::RegisterBlock, 0x4402_0000>;
impl core::fmt::Debug for FMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMC").finish()
    }
}
///FMC
pub mod fmc;
///FMC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC)
pub type SEC_FMC = crate::Periph<fmc::RegisterBlock, 0x5402_0000>;
impl core::fmt::Debug for SEC_FMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_FMC").finish()
    }
}
///FMC
pub use self::fmc as sec_fmc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4202_0000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOA)
pub type SEC_GPIOA = crate::Periph<gpioa::RegisterBlock, 0x5202_0000>;
impl core::fmt::Debug for SEC_GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOA").finish()
    }
}
///General-purpose I/Os
pub use self::gpioa as sec_gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4202_0400>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///General-purpose I/Os
pub mod gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOB)
pub type SEC_GPIOB = crate::Periph<gpiob::RegisterBlock, 0x5202_0400>;
impl core::fmt::Debug for SEC_GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOB").finish()
    }
}
///General-purpose I/Os
pub use self::gpiob as sec_gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4202_0800>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///General-purpose I/Os
pub mod gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4202_0c00>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4202_1000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4202_1400>;
impl core::fmt::Debug for GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOF").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiof;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4202_1800>;
impl core::fmt::Debug for GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOG").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiog;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type SEC_GPIOC = crate::Periph<gpioc::RegisterBlock, 0x5202_0800>;
impl core::fmt::Debug for SEC_GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOC").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as sec_gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type SEC_GPIOD = crate::Periph<gpioc::RegisterBlock, 0x5202_0c00>;
impl core::fmt::Debug for SEC_GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as sec_gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type SEC_GPIOE = crate::Periph<gpioc::RegisterBlock, 0x5202_1000>;
impl core::fmt::Debug for SEC_GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as sec_gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type SEC_GPIOF = crate::Periph<gpioc::RegisterBlock, 0x5202_1400>;
impl core::fmt::Debug for SEC_GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOF").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as sec_gpiof;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOC)
pub type SEC_GPIOG = crate::Periph<gpioc::RegisterBlock, 0x5202_1800>;
impl core::fmt::Debug for SEC_GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOG").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as sec_gpiog;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOH)
pub type GPIOH = crate::Periph<gpioh::RegisterBlock, 0x4202_1c00>;
impl core::fmt::Debug for GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOH").finish()
    }
}
///General-purpose I/Os
pub mod gpioh;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GPIOH)
pub type SEC_GPIOH = crate::Periph<gpioh::RegisterBlock, 0x5202_1c00>;
impl core::fmt::Debug for SEC_GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GPIOH").finish()
    }
}
///General-purpose I/Os
pub use self::gpioh as sec_gpioh;
///GTZC_MPCBB1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_MPCBB1)
pub type GTZC_MPCBB1 = crate::Periph<gtzc_mpcbb1::RegisterBlock, 0x4003_2c00>;
impl core::fmt::Debug for GTZC_MPCBB1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GTZC_MPCBB1").finish()
    }
}
///GTZC_MPCBB1
pub mod gtzc_mpcbb1;
///SEC_GTZC_MPCBB1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_MPCBB1)
pub type SEC_GTZC_MPCBB1 = crate::Periph<gtzc_mpcbb1::RegisterBlock, 0x5003_2c00>;
impl core::fmt::Debug for SEC_GTZC_MPCBB1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GTZC_MPCBB1").finish()
    }
}
///SEC_GTZC_MPCBB1
pub use self::gtzc_mpcbb1 as sec_gtzc_mpcbb1;
///GTZC_MPCBB2
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_MPCBB2)
pub type GTZC_MPCBB2 = crate::Periph<gtzc_mpcbb2::RegisterBlock, 0x4003_3000>;
impl core::fmt::Debug for GTZC_MPCBB2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GTZC_MPCBB2").finish()
    }
}
///GTZC_MPCBB2
pub mod gtzc_mpcbb2;
///SEC_GTZC_MPCBB2
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_MPCBB2)
pub type SEC_GTZC_MPCBB2 = crate::Periph<gtzc_mpcbb2::RegisterBlock, 0x5003_3000>;
impl core::fmt::Debug for SEC_GTZC_MPCBB2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GTZC_MPCBB2").finish()
    }
}
///SEC_GTZC_MPCBB2
pub use self::gtzc_mpcbb2 as sec_gtzc_mpcbb2;
///GTZC_TZIC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_TZIC)
pub type GTZC_TZIC = crate::Periph<gtzc_tzic::RegisterBlock, 0x4003_2800>;
impl core::fmt::Debug for GTZC_TZIC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GTZC_TZIC").finish()
    }
}
///GTZC_TZIC
pub mod gtzc_tzic;
///GTZC_TZIC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_TZIC)
pub type SEC_GTZC_TZIC = crate::Periph<gtzc_tzic::RegisterBlock, 0x5003_2800>;
impl core::fmt::Debug for SEC_GTZC_TZIC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GTZC_TZIC").finish()
    }
}
///GTZC_TZIC
pub use self::gtzc_tzic as sec_gtzc_tzic;
///GTZC_TZSC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_TZSC)
pub type GTZC_TZSC = crate::Periph<gtzc_tzsc::RegisterBlock, 0x4003_2400>;
impl core::fmt::Debug for GTZC_TZSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GTZC_TZSC").finish()
    }
}
///GTZC_TZSC
pub mod gtzc_tzsc;
///GTZC_TZSC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#GTZC_TZSC)
pub type SEC_GTZC_TZSC = crate::Periph<gtzc_tzsc::RegisterBlock, 0x5003_2400>;
impl core::fmt::Debug for SEC_GTZC_TZSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_GTZC_TZSC").finish()
    }
}
///GTZC_TZSC
pub use self::gtzc_tzsc as sec_gtzc_tzsc;
///Hash processor
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#HASH)
pub type HASH = crate::Periph<hash::RegisterBlock, 0x420c_0400>;
impl core::fmt::Debug for HASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HASH").finish()
    }
}
///Hash processor
pub mod hash;
///Hash processor
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#HASH)
pub type SEC_HASH = crate::Periph<hash::RegisterBlock, 0x520c_0400>;
impl core::fmt::Debug for SEC_HASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_HASH").finish()
    }
}
///Hash processor
pub use self::hash as sec_hash;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type I2C4 = crate::Periph<i2c1::RegisterBlock, 0x4000_8400>;
impl core::fmt::Debug for I2C4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C4").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c4;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type SEC_I2C1 = crate::Periph<i2c1::RegisterBlock, 0x5000_5400>;
impl core::fmt::Debug for SEC_I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_I2C1").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as sec_i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type SEC_I2C2 = crate::Periph<i2c1::RegisterBlock, 0x5000_5800>;
impl core::fmt::Debug for SEC_I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as sec_i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type SEC_I2C3 = crate::Periph<i2c1::RegisterBlock, 0x5000_5c00>;
impl core::fmt::Debug for SEC_I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as sec_i2c3;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#I2C1)
pub type SEC_I2C4 = crate::Periph<i2c1::RegisterBlock, 0x5000_8400>;
impl core::fmt::Debug for SEC_I2C4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_I2C4").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as sec_i2c4;
///ICache
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ICACHE)
pub type ICACHE = crate::Periph<icache::RegisterBlock, 0x4003_0400>;
impl core::fmt::Debug for ICACHE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ICACHE").finish()
    }
}
///ICache
pub mod icache;
///ICache
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#ICACHE)
pub type SEC_ICACHE = crate::Periph<icache::RegisterBlock, 0x5003_0400>;
impl core::fmt::Debug for SEC_ICACHE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_ICACHE").finish()
    }
}
///ICache
pub use self::icache as sec_icache;
///Independent watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#IWDG)
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG").finish()
    }
}
///Independent watchdog
pub mod iwdg;
///Independent watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#IWDG)
pub type SEC_IWDG = crate::Periph<iwdg::RegisterBlock, 0x5000_3000>;
impl core::fmt::Debug for SEC_IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_IWDG").finish()
    }
}
///Independent watchdog
pub use self::iwdg as sec_iwdg;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_7c00>;
impl core::fmt::Debug for LPTIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM1").finish()
    }
}
///Low power timer
pub mod lptim1;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x4000_9400>;
impl core::fmt::Debug for LPTIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM2").finish()
    }
}
///Low power timer
pub use self::lptim1 as lptim2;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type LPTIM3 = crate::Periph<lptim1::RegisterBlock, 0x4000_9800>;
impl core::fmt::Debug for LPTIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM3").finish()
    }
}
///Low power timer
pub use self::lptim1 as lptim3;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type SEC_LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x5000_7c00>;
impl core::fmt::Debug for SEC_LPTIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_LPTIM1").finish()
    }
}
///Low power timer
pub use self::lptim1 as sec_lptim1;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type SEC_LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x5000_9400>;
impl core::fmt::Debug for SEC_LPTIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_LPTIM2").finish()
    }
}
///Low power timer
pub use self::lptim1 as sec_lptim2;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPTIM1)
pub type SEC_LPTIM3 = crate::Periph<lptim1::RegisterBlock, 0x5000_9800>;
impl core::fmt::Debug for SEC_LPTIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_LPTIM3").finish()
    }
}
///Low power timer
pub use self::lptim1 as sec_lptim3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPUART1)
pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for LPUART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPUART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod lpuart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#LPUART1)
pub type SEC_LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x5000_8000>;
impl core::fmt::Debug for SEC_LPUART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_LPUART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::lpuart1 as sec_lpuart1;
///OctoSPI
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#OCTOSPI1)
pub type OCTOSPI1 = crate::Periph<octospi1::RegisterBlock, 0x4402_1000>;
impl core::fmt::Debug for OCTOSPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OCTOSPI1").finish()
    }
}
///OctoSPI
pub mod octospi1;
///OctoSPI
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#OCTOSPI1)
pub type SEC_OCTOSPI1 = crate::Periph<octospi1::RegisterBlock, 0x5402_1000>;
impl core::fmt::Debug for SEC_OCTOSPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_OCTOSPI1").finish()
    }
}
///OctoSPI
pub use self::octospi1 as sec_octospi1;
///Operational amplifiers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#OPAMP)
pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for OPAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP").finish()
    }
}
///Operational amplifiers
pub mod opamp;
///Operational amplifiers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#OPAMP)
pub type SEC_OPAMP = crate::Periph<opamp::RegisterBlock, 0x5000_7800>;
impl core::fmt::Debug for SEC_OPAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_OPAMP").finish()
    }
}
///Operational amplifiers
pub use self::opamp as sec_opamp;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///Power control
pub mod pwr;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#PWR)
pub type SEC_PWR = crate::Periph<pwr::RegisterBlock, 0x5000_7000>;
impl core::fmt::Debug for SEC_PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_PWR").finish()
    }
}
///Power control
pub use self::pwr as sec_pwr;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///Reset and clock control
pub mod rcc;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RCC)
pub type SEC_RCC = crate::Periph<rcc::RegisterBlock, 0x5002_1000>;
impl core::fmt::Debug for SEC_RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_RCC").finish()
    }
}
///Reset and clock control
pub use self::rcc as sec_rcc;
///RNG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RNG)
pub type RNG = crate::Periph<rng::RegisterBlock, 0x420c_0800>;
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
///RNG
pub mod rng;
///RNG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RNG)
pub type SEC_RNG = crate::Periph<rng::RegisterBlock, 0x520c_0800>;
impl core::fmt::Debug for SEC_RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_RNG").finish()
    }
}
///RNG
pub use self::rng as sec_rng;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///Real-time clock
pub mod rtc;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#RTC)
pub type SEC_RTC = crate::Periph<rtc::RegisterBlock, 0x5000_2800>;
impl core::fmt::Debug for SEC_RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_RTC").finish()
    }
}
///Real-time clock
pub use self::rtc as sec_rtc;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SAI1)
pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for SAI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI1").finish()
    }
}
///Serial audio interface
pub mod sai1;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SAI1)
pub type SAI2 = crate::Periph<sai1::RegisterBlock, 0x4001_5800>;
impl core::fmt::Debug for SAI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI2").finish()
    }
}
///Serial audio interface
pub use self::sai1 as sai2;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SAI1)
pub type SEC_SAI1 = crate::Periph<sai1::RegisterBlock, 0x5001_5400>;
impl core::fmt::Debug for SEC_SAI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SAI1").finish()
    }
}
///Serial audio interface
pub use self::sai1 as sec_sai1;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SAI1)
pub type SEC_SAI2 = crate::Periph<sai1::RegisterBlock, 0x5001_5800>;
impl core::fmt::Debug for SEC_SAI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SAI2").finish()
    }
}
///Serial audio interface
pub use self::sai1 as sec_sai2;
///SDMMC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SDMMC1)
pub type SDMMC1 = crate::Periph<sdmmc1::RegisterBlock, 0x420c_8000>;
impl core::fmt::Debug for SDMMC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDMMC1").finish()
    }
}
///SDMMC1
pub mod sdmmc1;
///SDMMC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SDMMC1)
pub type SEC_SDMMC1 = crate::Periph<sdmmc1::RegisterBlock, 0x520c_8000>;
impl core::fmt::Debug for SEC_SDMMC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SDMMC1").finish()
    }
}
///SDMMC1
pub use self::sdmmc1 as sec_sdmmc1;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///Serial peripheral interface
pub mod spi1;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi2;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi3;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SEC_SPI1 = crate::Periph<spi1::RegisterBlock, 0x5001_3000>;
impl core::fmt::Debug for SEC_SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SPI1").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as sec_spi1;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SEC_SPI2 = crate::Periph<spi1::RegisterBlock, 0x5000_3800>;
impl core::fmt::Debug for SEC_SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SPI2").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as sec_spi2;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SPI1)
pub type SEC_SPI3 = crate::Periph<spi1::RegisterBlock, 0x5000_3c00>;
impl core::fmt::Debug for SEC_SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SPI3").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as sec_spi3;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///System configuration controller
pub mod syscfg;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#SYSCFG)
pub type SEC_SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x5001_0000>;
impl core::fmt::Debug for SEC_SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_SYSCFG").finish()
    }
}
///System configuration controller
pub use self::syscfg as sec_syscfg;
///Tamper and backup registers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TAMP)
pub type TAMP = crate::Periph<tamp::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for TAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TAMP").finish()
    }
}
///Tamper and backup registers
pub mod tamp;
///Tamper and backup registers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TAMP)
pub type SEC_TAMP = crate::Periph<tamp::RegisterBlock, 0x5000_3400>;
impl core::fmt::Debug for SEC_TAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TAMP").finish()
    }
}
///Tamper and backup registers
pub use self::tamp as sec_tamp;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///Advanced-timers
pub mod tim1;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM1)
pub type SEC_TIM1 = crate::Periph<tim1::RegisterBlock, 0x5001_2c00>;
impl core::fmt::Debug for SEC_TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM1").finish()
    }
}
///Advanced-timers
pub use self::tim1 as sec_tim1;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///General-purpose-timers
pub mod tim2;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM2)
pub type SEC_TIM2 = crate::Periph<tim2::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for SEC_TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM2").finish()
    }
}
///General-purpose-timers
pub use self::tim2 as sec_tim2;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM3)
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM3").finish()
    }
}
///General-purpose-timers
pub mod tim3;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM3)
pub type SEC_TIM3 = crate::Periph<tim3::RegisterBlock, 0x5000_0400>;
impl core::fmt::Debug for SEC_TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM3").finish()
    }
}
///General-purpose-timers
pub use self::tim3 as sec_tim3;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM3)
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM4").finish()
    }
}
///General-purpose-timers
pub use self::tim3 as tim4;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM3)
pub type SEC_TIM4 = crate::Periph<tim3::RegisterBlock, 0x5000_0800>;
impl core::fmt::Debug for SEC_TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM4").finish()
    }
}
///General-purpose-timers
pub use self::tim3 as sec_tim4;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM2)
pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
impl core::fmt::Debug for TIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM5").finish()
    }
}
///General-purpose-timers
pub use self::tim2 as tim5;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM2)
pub type SEC_TIM5 = crate::Periph<tim2::RegisterBlock, 0x5000_0c00>;
impl core::fmt::Debug for SEC_TIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM5").finish()
    }
}
///General-purpose-timers
pub use self::tim2 as sec_tim5;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM6)
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///General-purpose-timers
pub mod tim6;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM6)
pub type SEC_TIM6 = crate::Periph<tim6::RegisterBlock, 0x5000_1000>;
impl core::fmt::Debug for SEC_TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM6").finish()
    }
}
///General-purpose-timers
pub use self::tim6 as sec_tim6;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM6)
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///General-purpose-timers
pub use self::tim6 as tim7;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM6)
pub type SEC_TIM7 = crate::Periph<tim6::RegisterBlock, 0x5000_1400>;
impl core::fmt::Debug for SEC_TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM7").finish()
    }
}
///General-purpose-timers
pub use self::tim6 as sec_tim7;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM8)
pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM8").finish()
    }
}
///Advanced-timers
pub mod tim8;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM8)
pub type SEC_TIM8 = crate::Periph<tim8::RegisterBlock, 0x5001_3400>;
impl core::fmt::Debug for SEC_TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM8").finish()
    }
}
///Advanced-timers
pub use self::tim8 as sec_tim8;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM15)
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM15").finish()
    }
}
///General purpose timers
pub mod tim15;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM15)
pub type SEC_TIM15 = crate::Periph<tim15::RegisterBlock, 0x5001_4000>;
impl core::fmt::Debug for SEC_TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM15").finish()
    }
}
///General purpose timers
pub use self::tim15 as sec_tim15;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM16)
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM16").finish()
    }
}
///General purpose timers
pub mod tim16;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM16)
pub type SEC_TIM16 = crate::Periph<tim16::RegisterBlock, 0x5001_4400>;
impl core::fmt::Debug for SEC_TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM16").finish()
    }
}
///General purpose timers
pub use self::tim16 as sec_tim16;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM17)
pub type TIM17 = crate::Periph<tim17::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM17").finish()
    }
}
///General purpose timers
pub mod tim17;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TIM17)
pub type SEC_TIM17 = crate::Periph<tim17::RegisterBlock, 0x5001_4800>;
impl core::fmt::Debug for SEC_TIM17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TIM17").finish()
    }
}
///General purpose timers
pub use self::tim17 as sec_tim17;
///Touch sensing controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TSC)
pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for TSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TSC").finish()
    }
}
///Touch sensing controller
pub mod tsc;
///Touch sensing controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#TSC)
pub type SEC_TSC = crate::Periph<tsc::RegisterBlock, 0x5002_4000>;
impl core::fmt::Debug for SEC_TSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_TSC").finish()
    }
}
///Touch sensing controller
pub use self::tsc as sec_tsc;
///Universal serial bus full-speed device interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USB)
pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_d400>;
impl core::fmt::Debug for USB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB").finish()
    }
}
///Universal serial bus full-speed device interface
pub mod usb;
///Universal serial bus full-speed device interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USB)
pub type SEC_USB = crate::Periph<usb::RegisterBlock, 0x5000_d400>;
impl core::fmt::Debug for SEC_USB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_USB").finish()
    }
}
///Universal serial bus full-speed device interface
pub use self::usb as sec_usb;
///USB Power Delivery interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#UCPD1)
pub type UCPD1 = crate::Periph<ucpd1::RegisterBlock, 0x4000_dc00>;
impl core::fmt::Debug for UCPD1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UCPD1").finish()
    }
}
///USB Power Delivery interface
pub mod ucpd1;
///USB Power Delivery interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#UCPD1)
pub type SEC_UCPD1 = crate::Periph<ucpd1::RegisterBlock, 0x5000_dc00>;
impl core::fmt::Debug for SEC_UCPD1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_UCPD1").finish()
    }
}
///USB Power Delivery interface
pub use self::ucpd1 as sec_ucpd1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type SEC_USART1 = crate::Periph<usart1::RegisterBlock, 0x5001_3800>;
impl core::fmt::Debug for SEC_USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as sec_usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type SEC_USART2 = crate::Periph<usart1::RegisterBlock, 0x5000_4400>;
impl core::fmt::Debug for SEC_USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as sec_usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type SEC_USART3 = crate::Periph<usart1::RegisterBlock, 0x5000_4800>;
impl core::fmt::Debug for SEC_USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as sec_usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as uart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type UART5 = crate::Periph<usart1::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as uart5;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type SEC_UART4 = crate::Periph<usart1::RegisterBlock, 0x5000_4c00>;
impl core::fmt::Debug for SEC_UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_UART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as sec_uart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#USART1)
pub type SEC_UART5 = crate::Periph<usart1::RegisterBlock, 0x5000_5000>;
impl core::fmt::Debug for SEC_UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_UART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as sec_uart5;
///Voltage reference buffer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#VREFBUF)
pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x4001_0030>;
impl core::fmt::Debug for VREFBUF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("VREFBUF").finish()
    }
}
///Voltage reference buffer
pub mod vrefbuf;
///Voltage reference buffer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#VREFBUF)
pub type SEC_VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x5001_0030>;
impl core::fmt::Debug for SEC_VREFBUF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_VREFBUF").finish()
    }
}
///Voltage reference buffer
pub use self::vrefbuf as sec_vrefbuf;
///System window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#WWDG)
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG").finish()
    }
}
///System window watchdog
pub mod wwdg;
///System window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#WWDG)
pub type SEC_WWDG = crate::Periph<wwdg::RegisterBlock, 0x5000_2c00>;
impl core::fmt::Debug for SEC_WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC_WWDG").finish()
    }
}
///System window watchdog
pub use self::wwdg as sec_wwdg;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///ADC1
    pub ADC1: ADC1,
    ///SEC_ADC1
    pub SEC_ADC1: SEC_ADC1,
    ///ADC2
    pub ADC2: ADC2,
    ///SEC_ADC2
    pub SEC_ADC2: SEC_ADC2,
    ///ADC_Common
    pub ADC_COMMON: ADC_COMMON,
    ///SEC_ADC_Common
    pub SEC_ADC_COMMON: SEC_ADC_COMMON,
    ///COMP
    pub COMP: COMP,
    ///SEC_COMP
    pub SEC_COMP: SEC_COMP,
    ///CRC
    pub CRC: CRC,
    ///SEC_CRC
    pub SEC_CRC: SEC_CRC,
    ///CRS
    pub CRS: CRS,
    ///SEC_CRS
    pub SEC_CRS: SEC_CRS,
    ///DAC
    pub DAC: DAC,
    ///SEC_DAC
    pub SEC_DAC: SEC_DAC,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
    ///DFSDM1
    pub DFSDM1: DFSDM1,
    ///SEC_DFSDM1
    pub SEC_DFSDM1: SEC_DFSDM1,
    ///DMA1
    pub DMA1: DMA1,
    ///SEC_DMA1
    pub SEC_DMA1: SEC_DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///SEC_DMA2
    pub SEC_DMA2: SEC_DMA2,
    ///DMAMUX1
    pub DMAMUX1: DMAMUX1,
    ///SEC_DMAMUX1
    pub SEC_DMAMUX1: SEC_DMAMUX1,
    ///EXTI
    pub EXTI: EXTI,
    ///SEC_EXTI
    pub SEC_EXTI: SEC_EXTI,
    ///FDCAN1
    pub FDCAN1: FDCAN1,
    ///SEC_FDCAN1
    pub SEC_FDCAN1: SEC_FDCAN1,
    ///FLASH
    pub FLASH: FLASH,
    ///SEC_FLASH
    pub SEC_FLASH: SEC_FLASH,
    ///FMC
    pub FMC: FMC,
    ///SEC_FMC
    pub SEC_FMC: SEC_FMC,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///SEC_GPIOA
    pub SEC_GPIOA: SEC_GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///SEC_GPIOB
    pub SEC_GPIOB: SEC_GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOF
    pub GPIOF: GPIOF,
    ///GPIOG
    pub GPIOG: GPIOG,
    ///SEC_GPIOC
    pub SEC_GPIOC: SEC_GPIOC,
    ///SEC_GPIOD
    pub SEC_GPIOD: SEC_GPIOD,
    ///SEC_GPIOE
    pub SEC_GPIOE: SEC_GPIOE,
    ///SEC_GPIOF
    pub SEC_GPIOF: SEC_GPIOF,
    ///SEC_GPIOG
    pub SEC_GPIOG: SEC_GPIOG,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///SEC_GPIOH
    pub SEC_GPIOH: SEC_GPIOH,
    ///GTZC_MPCBB1
    pub GTZC_MPCBB1: GTZC_MPCBB1,
    ///SEC_GTZC_MPCBB1
    pub SEC_GTZC_MPCBB1: SEC_GTZC_MPCBB1,
    ///GTZC_MPCBB2
    pub GTZC_MPCBB2: GTZC_MPCBB2,
    ///SEC_GTZC_MPCBB2
    pub SEC_GTZC_MPCBB2: SEC_GTZC_MPCBB2,
    ///GTZC_TZIC
    pub GTZC_TZIC: GTZC_TZIC,
    ///SEC_GTZC_TZIC
    pub SEC_GTZC_TZIC: SEC_GTZC_TZIC,
    ///GTZC_TZSC
    pub GTZC_TZSC: GTZC_TZSC,
    ///SEC_GTZC_TZSC
    pub SEC_GTZC_TZSC: SEC_GTZC_TZSC,
    ///HASH
    pub HASH: HASH,
    ///SEC_HASH
    pub SEC_HASH: SEC_HASH,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///I2C4
    pub I2C4: I2C4,
    ///SEC_I2C1
    pub SEC_I2C1: SEC_I2C1,
    ///SEC_I2C2
    pub SEC_I2C2: SEC_I2C2,
    ///SEC_I2C3
    pub SEC_I2C3: SEC_I2C3,
    ///SEC_I2C4
    pub SEC_I2C4: SEC_I2C4,
    ///ICACHE
    pub ICACHE: ICACHE,
    ///SEC_ICache
    pub SEC_ICACHE: SEC_ICACHE,
    ///IWDG
    pub IWDG: IWDG,
    ///SEC_IWDG
    pub SEC_IWDG: SEC_IWDG,
    ///LPTIM1
    pub LPTIM1: LPTIM1,
    ///LPTIM2
    pub LPTIM2: LPTIM2,
    ///LPTIM3
    pub LPTIM3: LPTIM3,
    ///SEC_LPTIM1
    pub SEC_LPTIM1: SEC_LPTIM1,
    ///SEC_LPTIM2
    pub SEC_LPTIM2: SEC_LPTIM2,
    ///SEC_LPTIM3
    pub SEC_LPTIM3: SEC_LPTIM3,
    ///LPUART1
    pub LPUART1: LPUART1,
    ///SEC_LPUART1
    pub SEC_LPUART1: SEC_LPUART1,
    ///OCTOSPI1
    pub OCTOSPI1: OCTOSPI1,
    ///SEC_OCTOSPI1
    pub SEC_OCTOSPI1: SEC_OCTOSPI1,
    ///OPAMP
    pub OPAMP: OPAMP,
    ///SEC_OPAMP
    pub SEC_OPAMP: SEC_OPAMP,
    ///PWR
    pub PWR: PWR,
    ///SEC_PWR
    pub SEC_PWR: SEC_PWR,
    ///RCC
    pub RCC: RCC,
    ///SEC_RCC
    pub SEC_RCC: SEC_RCC,
    ///RNG
    pub RNG: RNG,
    ///SEC_RNG
    pub SEC_RNG: SEC_RNG,
    ///RTC
    pub RTC: RTC,
    ///SEC_RTC
    pub SEC_RTC: SEC_RTC,
    ///SAI1
    pub SAI1: SAI1,
    ///SAI2
    pub SAI2: SAI2,
    ///SEC_SAI1
    pub SEC_SAI1: SEC_SAI1,
    ///SEC_SAI2
    pub SEC_SAI2: SEC_SAI2,
    ///SDMMC1
    pub SDMMC1: SDMMC1,
    ///SEC_SDMMC1
    pub SEC_SDMMC1: SEC_SDMMC1,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI2
    pub SPI2: SPI2,
    ///SPI3
    pub SPI3: SPI3,
    ///SEC_SPI1
    pub SEC_SPI1: SEC_SPI1,
    ///SEC_SPI2
    pub SEC_SPI2: SEC_SPI2,
    ///SEC_SPI3
    pub SEC_SPI3: SEC_SPI3,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///SEC_SYSCFG
    pub SEC_SYSCFG: SEC_SYSCFG,
    ///TAMP
    pub TAMP: TAMP,
    ///SEC_TAMP
    pub SEC_TAMP: SEC_TAMP,
    ///TIM1
    pub TIM1: TIM1,
    ///SEC_TIM1
    pub SEC_TIM1: SEC_TIM1,
    ///TIM2
    pub TIM2: TIM2,
    ///SEC_TIM2
    pub SEC_TIM2: SEC_TIM2,
    ///TIM3
    pub TIM3: TIM3,
    ///SEC_TIM3
    pub SEC_TIM3: SEC_TIM3,
    ///TIM4
    pub TIM4: TIM4,
    ///SEC_TIM4
    pub SEC_TIM4: SEC_TIM4,
    ///TIM5
    pub TIM5: TIM5,
    ///SEC_TIM5
    pub SEC_TIM5: SEC_TIM5,
    ///TIM6
    pub TIM6: TIM6,
    ///SEC_TIM6
    pub SEC_TIM6: SEC_TIM6,
    ///TIM7
    pub TIM7: TIM7,
    ///SEC_TIM7
    pub SEC_TIM7: SEC_TIM7,
    ///TIM8
    pub TIM8: TIM8,
    ///SEC_TIM8
    pub SEC_TIM8: SEC_TIM8,
    ///TIM15
    pub TIM15: TIM15,
    ///SEC_TIM15
    pub SEC_TIM15: SEC_TIM15,
    ///TIM16
    pub TIM16: TIM16,
    ///SEC_TIM16
    pub SEC_TIM16: SEC_TIM16,
    ///TIM17
    pub TIM17: TIM17,
    ///SEC_TIM17
    pub SEC_TIM17: SEC_TIM17,
    ///TSC
    pub TSC: TSC,
    ///SEC_TSC
    pub SEC_TSC: SEC_TSC,
    ///USB
    pub USB: USB,
    ///SEC_USB
    pub SEC_USB: SEC_USB,
    ///UCPD1
    pub UCPD1: UCPD1,
    ///SEC_UCPD1
    pub SEC_UCPD1: SEC_UCPD1,
    ///USART1
    pub USART1: USART1,
    ///SEC_USART1
    pub SEC_USART1: SEC_USART1,
    ///USART2
    pub USART2: USART2,
    ///SEC_USART2
    pub SEC_USART2: SEC_USART2,
    ///USART3
    pub USART3: USART3,
    ///SEC_USART3
    pub SEC_USART3: SEC_USART3,
    ///UART4
    pub UART4: UART4,
    ///UART5
    pub UART5: UART5,
    ///SEC_UART4
    pub SEC_UART4: SEC_UART4,
    ///SEC_UART5
    pub SEC_UART5: SEC_UART5,
    ///VREFBUF
    pub VREFBUF: VREFBUF,
    ///SEC_VREFBUF
    pub SEC_VREFBUF: SEC_VREFBUF,
    ///WWDG
    pub WWDG: WWDG,
    ///SEC_WWDG
    pub SEC_WWDG: SEC_WWDG,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            ADC1: ADC1::steal(),
            SEC_ADC1: SEC_ADC1::steal(),
            ADC2: ADC2::steal(),
            SEC_ADC2: SEC_ADC2::steal(),
            ADC_COMMON: ADC_COMMON::steal(),
            SEC_ADC_COMMON: SEC_ADC_COMMON::steal(),
            COMP: COMP::steal(),
            SEC_COMP: SEC_COMP::steal(),
            CRC: CRC::steal(),
            SEC_CRC: SEC_CRC::steal(),
            CRS: CRS::steal(),
            SEC_CRS: SEC_CRS::steal(),
            DAC: DAC::steal(),
            SEC_DAC: SEC_DAC::steal(),
            DBGMCU: DBGMCU::steal(),
            DFSDM1: DFSDM1::steal(),
            SEC_DFSDM1: SEC_DFSDM1::steal(),
            DMA1: DMA1::steal(),
            SEC_DMA1: SEC_DMA1::steal(),
            DMA2: DMA2::steal(),
            SEC_DMA2: SEC_DMA2::steal(),
            DMAMUX1: DMAMUX1::steal(),
            SEC_DMAMUX1: SEC_DMAMUX1::steal(),
            EXTI: EXTI::steal(),
            SEC_EXTI: SEC_EXTI::steal(),
            FDCAN1: FDCAN1::steal(),
            SEC_FDCAN1: SEC_FDCAN1::steal(),
            FLASH: FLASH::steal(),
            SEC_FLASH: SEC_FLASH::steal(),
            FMC: FMC::steal(),
            SEC_FMC: SEC_FMC::steal(),
            GPIOA: GPIOA::steal(),
            SEC_GPIOA: SEC_GPIOA::steal(),
            GPIOB: GPIOB::steal(),
            SEC_GPIOB: SEC_GPIOB::steal(),
            GPIOC: GPIOC::steal(),
            GPIOD: GPIOD::steal(),
            GPIOE: GPIOE::steal(),
            GPIOF: GPIOF::steal(),
            GPIOG: GPIOG::steal(),
            SEC_GPIOC: SEC_GPIOC::steal(),
            SEC_GPIOD: SEC_GPIOD::steal(),
            SEC_GPIOE: SEC_GPIOE::steal(),
            SEC_GPIOF: SEC_GPIOF::steal(),
            SEC_GPIOG: SEC_GPIOG::steal(),
            GPIOH: GPIOH::steal(),
            SEC_GPIOH: SEC_GPIOH::steal(),
            GTZC_MPCBB1: GTZC_MPCBB1::steal(),
            SEC_GTZC_MPCBB1: SEC_GTZC_MPCBB1::steal(),
            GTZC_MPCBB2: GTZC_MPCBB2::steal(),
            SEC_GTZC_MPCBB2: SEC_GTZC_MPCBB2::steal(),
            GTZC_TZIC: GTZC_TZIC::steal(),
            SEC_GTZC_TZIC: SEC_GTZC_TZIC::steal(),
            GTZC_TZSC: GTZC_TZSC::steal(),
            SEC_GTZC_TZSC: SEC_GTZC_TZSC::steal(),
            HASH: HASH::steal(),
            SEC_HASH: SEC_HASH::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            I2C4: I2C4::steal(),
            SEC_I2C1: SEC_I2C1::steal(),
            SEC_I2C2: SEC_I2C2::steal(),
            SEC_I2C3: SEC_I2C3::steal(),
            SEC_I2C4: SEC_I2C4::steal(),
            ICACHE: ICACHE::steal(),
            SEC_ICACHE: SEC_ICACHE::steal(),
            IWDG: IWDG::steal(),
            SEC_IWDG: SEC_IWDG::steal(),
            LPTIM1: LPTIM1::steal(),
            LPTIM2: LPTIM2::steal(),
            LPTIM3: LPTIM3::steal(),
            SEC_LPTIM1: SEC_LPTIM1::steal(),
            SEC_LPTIM2: SEC_LPTIM2::steal(),
            SEC_LPTIM3: SEC_LPTIM3::steal(),
            LPUART1: LPUART1::steal(),
            SEC_LPUART1: SEC_LPUART1::steal(),
            OCTOSPI1: OCTOSPI1::steal(),
            SEC_OCTOSPI1: SEC_OCTOSPI1::steal(),
            OPAMP: OPAMP::steal(),
            SEC_OPAMP: SEC_OPAMP::steal(),
            PWR: PWR::steal(),
            SEC_PWR: SEC_PWR::steal(),
            RCC: RCC::steal(),
            SEC_RCC: SEC_RCC::steal(),
            RNG: RNG::steal(),
            SEC_RNG: SEC_RNG::steal(),
            RTC: RTC::steal(),
            SEC_RTC: SEC_RTC::steal(),
            SAI1: SAI1::steal(),
            SAI2: SAI2::steal(),
            SEC_SAI1: SEC_SAI1::steal(),
            SEC_SAI2: SEC_SAI2::steal(),
            SDMMC1: SDMMC1::steal(),
            SEC_SDMMC1: SEC_SDMMC1::steal(),
            SPI1: SPI1::steal(),
            SPI2: SPI2::steal(),
            SPI3: SPI3::steal(),
            SEC_SPI1: SEC_SPI1::steal(),
            SEC_SPI2: SEC_SPI2::steal(),
            SEC_SPI3: SEC_SPI3::steal(),
            SYSCFG: SYSCFG::steal(),
            SEC_SYSCFG: SEC_SYSCFG::steal(),
            TAMP: TAMP::steal(),
            SEC_TAMP: SEC_TAMP::steal(),
            TIM1: TIM1::steal(),
            SEC_TIM1: SEC_TIM1::steal(),
            TIM2: TIM2::steal(),
            SEC_TIM2: SEC_TIM2::steal(),
            TIM3: TIM3::steal(),
            SEC_TIM3: SEC_TIM3::steal(),
            TIM4: TIM4::steal(),
            SEC_TIM4: SEC_TIM4::steal(),
            TIM5: TIM5::steal(),
            SEC_TIM5: SEC_TIM5::steal(),
            TIM6: TIM6::steal(),
            SEC_TIM6: SEC_TIM6::steal(),
            TIM7: TIM7::steal(),
            SEC_TIM7: SEC_TIM7::steal(),
            TIM8: TIM8::steal(),
            SEC_TIM8: SEC_TIM8::steal(),
            TIM15: TIM15::steal(),
            SEC_TIM15: SEC_TIM15::steal(),
            TIM16: TIM16::steal(),
            SEC_TIM16: SEC_TIM16::steal(),
            TIM17: TIM17::steal(),
            SEC_TIM17: SEC_TIM17::steal(),
            TSC: TSC::steal(),
            SEC_TSC: SEC_TSC::steal(),
            USB: USB::steal(),
            SEC_USB: SEC_USB::steal(),
            UCPD1: UCPD1::steal(),
            SEC_UCPD1: SEC_UCPD1::steal(),
            USART1: USART1::steal(),
            SEC_USART1: SEC_USART1::steal(),
            USART2: USART2::steal(),
            SEC_USART2: SEC_USART2::steal(),
            USART3: USART3::steal(),
            SEC_USART3: SEC_USART3::steal(),
            UART4: UART4::steal(),
            UART5: UART5::steal(),
            SEC_UART4: SEC_UART4::steal(),
            SEC_UART5: SEC_UART5::steal(),
            VREFBUF: VREFBUF::steal(),
            SEC_VREFBUF: SEC_VREFBUF::steal(),
            WWDG: WWDG::steal(),
            SEC_WWDG: SEC_WWDG::steal(),
        }
    }
}