#[repr(C)]
#[derive(Debug)]
///Register block
pub struct RegisterBlock {
bcr1: BCR1,
btr: (),
_reserved2: [u8; 0x04],
bcr: (),
_reserved3: [u8; 0x18],
pcscntr: PCSCNTR,
_reserved4: [u8; 0x5c],
pcr: PCR,
sr: SR,
pmem: PMEM,
patt: PATT,
_reserved8: [u8; 0x04],
eccr: ECCR,
_reserved9: [u8; 0x6c],
bwtr: (),
}
impl RegisterBlock {
///0x00 - FMC_BCR1
#[inline(always)]
pub const fn bcr1(&self) -> &BCR1 {
&self.bcr1
}
///0x04..0x14 - SRAM/NOR-flash chip-select timing registers for bank %s
///
///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BTR1` register.</div>
#[inline(always)]
pub const fn btr(&self, n: usize) -> &BTR {
#[allow(clippy::no_effect)]
[(); 4][n];
unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(4)
.add(8 * n)
.cast()
}
}
///Iterator for array of:
///0x04..0x14 - SRAM/NOR-flash chip-select timing registers for bank %s
#[inline(always)]
pub fn btr_iter(&self) -> impl Iterator<Item = &BTR> {
(0..4).map(move |n| unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(4)
.add(8 * n)
.cast()
})
}
///0x04 - SRAM/NOR-flash chip-select timing registers for bank 1
#[inline(always)]
pub const fn btr1(&self) -> &BTR {
self.btr(0)
}
///0x0c - SRAM/NOR-flash chip-select timing registers for bank 2
#[inline(always)]
pub const fn btr2(&self) -> &BTR {
self.btr(1)
}
///0x14 - SRAM/NOR-flash chip-select timing registers for bank 3
#[inline(always)]
pub const fn btr3(&self) -> &BTR {
self.btr(2)
}
///0x1c - SRAM/NOR-flash chip-select timing registers for bank 4
#[inline(always)]
pub const fn btr4(&self) -> &BTR {
self.btr(3)
}
///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
///
///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BCR2` register.</div>
#[inline(always)]
pub const fn bcr(&self, n: usize) -> &BCR {
#[allow(clippy::no_effect)]
[(); 3][n];
unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(8)
.add(8 * n)
.cast()
}
}
///Iterator for array of:
///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
#[inline(always)]
pub fn bcr_iter(&self) -> impl Iterator<Item = &BCR> {
(0..3).map(move |n| unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(8)
.add(8 * n)
.cast()
})
}
///0x08 - SRAM/NOR-Flash chip-select control register 2
#[inline(always)]
pub const fn bcr2(&self) -> &BCR {
self.bcr(0)
}
///0x10 - SRAM/NOR-Flash chip-select control register 3
#[inline(always)]
pub const fn bcr3(&self) -> &BCR {
self.bcr(1)
}
///0x18 - SRAM/NOR-Flash chip-select control register 4
#[inline(always)]
pub const fn bcr4(&self) -> &BCR {
self.bcr(2)
}
///0x20 - PCSCNTR
#[inline(always)]
pub const fn pcscntr(&self) -> &PCSCNTR {
&self.pcscntr
}
///0x80 - NAND Flash control registers
#[inline(always)]
pub const fn pcr(&self) -> &PCR {
&self.pcr
}
///0x84 - This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
#[inline(always)]
pub const fn sr(&self) -> &SR {
&self.sr
}
///0x88 - The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
#[inline(always)]
pub const fn pmem(&self) -> &PMEM {
&self.pmem
}
///0x8c - The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
#[inline(always)]
pub const fn patt(&self) -> &PATT {
&self.patt
}
///0x94 - This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
#[inline(always)]
pub const fn eccr(&self) -> &ECCR {
&self.eccr
}
///0x104..0x114 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
///
///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BWTR1` register.</div>
#[inline(always)]
pub const fn bwtr(&self, n: usize) -> &BWTR {
#[allow(clippy::no_effect)]
[(); 4][n];
unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(260)
.add(8 * n)
.cast()
}
}
///Iterator for array of:
///0x104..0x114 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
#[inline(always)]
pub fn bwtr_iter(&self) -> impl Iterator<Item = &BWTR> {
(0..4).map(move |n| unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(260)
.add(8 * n)
.cast()
})
}
///0x104 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
#[inline(always)]
pub const fn bwtr1(&self) -> &BWTR {
self.bwtr(0)
}
///0x10c - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
#[inline(always)]
pub const fn bwtr2(&self) -> &BWTR {
self.bwtr(1)
}
///0x114 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
#[inline(always)]
pub const fn bwtr3(&self) -> &BWTR {
self.bwtr(2)
}
///0x11c - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
#[inline(always)]
pub const fn bwtr4(&self) -> &BWTR {
self.bwtr(3)
}
}
/**BCR1 (rw) register accessor: FMC_BCR1
You can [`read`](crate::Reg::read) this register and get [`bcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:BCR1)
For information about available fields see [`mod@bcr1`] module*/
pub type BCR1 = crate::Reg<bcr1::BCR1rs>;
///FMC_BCR1
pub mod bcr1;
/**BCR (rw) register accessor: SRAM/NOR-Flash chip-select control register %s
You can [`read`](crate::Reg::read) this register and get [`bcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:BCR[2])
For information about available fields see [`mod@bcr`] module*/
pub type BCR = crate::Reg<bcr::BCRrs>;
///SRAM/NOR-Flash chip-select control register %s
pub mod bcr;
/**BTR (rw) register accessor: SRAM/NOR-flash chip-select timing registers for bank %s
You can [`read`](crate::Reg::read) this register and get [`btr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:BTR[1])
For information about available fields see [`mod@btr`] module*/
pub type BTR = crate::Reg<btr::BTRrs>;
///SRAM/NOR-flash chip-select timing registers for bank %s
pub mod btr;
/**PCR (rw) register accessor: NAND Flash control registers
You can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:PCR)
For information about available fields see [`mod@pcr`] module*/
pub type PCR = crate::Reg<pcr::PCRrs>;
///NAND Flash control registers
pub mod pcr;
/**SR (rw) register accessor: This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:SR)
For information about available fields see [`mod@sr`] module*/
pub type SR = crate::Reg<sr::SRrs>;
///This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
pub mod sr;
/**PMEM (rw) register accessor: The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
You can [`read`](crate::Reg::read) this register and get [`pmem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:PMEM)
For information about available fields see [`mod@pmem`] module*/
pub type PMEM = crate::Reg<pmem::PMEMrs>;
///The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
pub mod pmem;
/**PATT (rw) register accessor: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
You can [`read`](crate::Reg::read) this register and get [`patt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:PATT)
For information about available fields see [`mod@patt`] module*/
pub type PATT = crate::Reg<patt::PATTrs>;
///The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
pub mod patt;
/**ECCR (r) register accessor: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
You can [`read`](crate::Reg::read) this register and get [`eccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:ECCR)
For information about available fields see [`mod@eccr`] module*/
pub type ECCR = crate::Reg<eccr::ECCRrs>;
///This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
pub mod eccr;
/**BWTR (rw) register accessor: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
You can [`read`](crate::Reg::read) this register and get [`bwtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:BWTR[1])
For information about available fields see [`mod@bwtr`] module*/
pub type BWTR = crate::Reg<bwtr::BWTRrs>;
///This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
pub mod bwtr;
/**PCSCNTR (rw) register accessor: PCSCNTR
You can [`read`](crate::Reg::read) this register and get [`pcscntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcscntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L552.html#FMC:PCSCNTR)
For information about available fields see [`mod@pcscntr`] module*/
pub type PCSCNTR = crate::Reg<pcscntr::PCSCNTRrs>;
///PCSCNTR
pub mod pcscntr;