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///Register `CSR` reader
pub type R = crate::R<CSRrs>;
///Register `CSR` writer
pub type W = crate::W<CSRrs>;
/**LSI oscillator enable Set and reset by software.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LSION {
///0: LSI oscillator Off
Off = 0,
///1: LSI oscillator On
On = 1,
}
impl From<LSION> for bool {
#[inline(always)]
fn from(variant: LSION) -> Self {
variant as u8 != 0
}
}
///Field `LSION` reader - LSI oscillator enable Set and reset by software.
pub type LSION_R = crate::BitReader<LSION>;
impl LSION_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> LSION {
match self.bits {
false => LSION::Off,
true => LSION::On,
}
}
///LSI oscillator Off
#[inline(always)]
pub fn is_off(&self) -> bool {
*self == LSION::Off
}
///LSI oscillator On
#[inline(always)]
pub fn is_on(&self) -> bool {
*self == LSION::On
}
}
///Field `LSION` writer - LSI oscillator enable Set and reset by software.
pub type LSION_W<'a, REG> = crate::BitWriter<'a, REG, LSION>;
impl<'a, REG> LSION_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///LSI oscillator Off
#[inline(always)]
pub fn off(self) -> &'a mut crate::W<REG> {
self.variant(LSION::Off)
}
///LSI oscillator On
#[inline(always)]
pub fn on(self) -> &'a mut crate::W<REG> {
self.variant(LSION::On)
}
}
/**LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LSIRDYR {
///0: LSI oscillator not ready
NotReady = 0,
///1: LSI oscillator ready
Ready = 1,
}
impl From<LSIRDYR> for bool {
#[inline(always)]
fn from(variant: LSIRDYR) -> Self {
variant as u8 != 0
}
}
///Field `LSIRDY` reader - LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.
pub type LSIRDY_R = crate::BitReader<LSIRDYR>;
impl LSIRDY_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> LSIRDYR {
match self.bits {
false => LSIRDYR::NotReady,
true => LSIRDYR::Ready,
}
}
///LSI oscillator not ready
#[inline(always)]
pub fn is_not_ready(&self) -> bool {
*self == LSIRDYR::NotReady
}
///LSI oscillator ready
#[inline(always)]
pub fn is_ready(&self) -> bool {
*self == LSIRDYR::Ready
}
}
impl R {
///Bit 0 - LSI oscillator enable Set and reset by software.
#[inline(always)]
pub fn lsion(&self) -> LSION_R {
LSION_R::new((self.bits & 1) != 0)
}
///Bit 1 - LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.
#[inline(always)]
pub fn lsirdy(&self) -> LSIRDY_R {
LSIRDY_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CSR")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.finish()
}
}
impl W {
///Bit 0 - LSI oscillator enable Set and reset by software.
#[inline(always)]
pub fn lsion(&mut self) -> LSION_W<CSRrs> {
LSION_W::new(self, 0)
}
}
/**RCC clock control and status register
You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CSRrs;
impl crate::RegisterSpec for CSRrs {
type Ux = u32;
}
///`read()` method returns [`csr::R`](R) reader structure
impl crate::Readable for CSRrs {}
///`write(|w| ..)` method takes [`csr::W`](W) writer structure
impl crate::Writable for CSRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets CSR to value 0
impl crate::Resettable for CSRrs {}