stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

///Register `AHB2RSTR` reader
pub type R = crate::R<AHB2RSTRrs>;
///Register `AHB2RSTR` writer
pub type W = crate::W<AHB2RSTRrs>;
/**digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DCMI_PSSIRST {
    ///1: Reset the selected module
    Reset = 1,
}
impl From<DCMI_PSSIRST> for bool {
    #[inline(always)]
    fn from(variant: DCMI_PSSIRST) -> Self {
        variant as u8 != 0
    }
}
///Field `DCMI_PSSIRST` reader - digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software.
pub type DCMI_PSSIRST_R = crate::BitReader<DCMI_PSSIRST>;
impl DCMI_PSSIRST_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<DCMI_PSSIRST> {
        match self.bits {
            true => Some(DCMI_PSSIRST::Reset),
            _ => None,
        }
    }
    ///Reset the selected module
    #[inline(always)]
    pub fn is_reset(&self) -> bool {
        *self == DCMI_PSSIRST::Reset
    }
}
///Field `DCMI_PSSIRST` writer - digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software.
pub type DCMI_PSSIRST_W<'a, REG> = crate::BitWriter<'a, REG, DCMI_PSSIRST>;
impl<'a, REG> DCMI_PSSIRST_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Reset the selected module
    #[inline(always)]
    pub fn reset(self) -> &'a mut crate::W<REG> {
        self.variant(DCMI_PSSIRST::Reset)
    }
}
///Field `HSEMRST` reader - HSEM block reset Set and reset by software.
pub use DCMI_PSSIRST_R as HSEMRST_R;
///Field `RNGRST` reader - random number generator block reset Set and reset by software.
pub use DCMI_PSSIRST_R as RNGRST_R;
///Field `SDMMC2RST` reader - SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
pub use DCMI_PSSIRST_R as SDMMC2RST_R;
///Field `BDMA1RST` reader - BDMA1 reset (DFSDM dedicated DMA) Set and reset by software.
pub use DCMI_PSSIRST_R as BDMA1RST_R;
///Field `HSEMRST` writer - HSEM block reset Set and reset by software.
pub use DCMI_PSSIRST_W as HSEMRST_W;
///Field `RNGRST` writer - random number generator block reset Set and reset by software.
pub use DCMI_PSSIRST_W as RNGRST_W;
///Field `SDMMC2RST` writer - SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
pub use DCMI_PSSIRST_W as SDMMC2RST_W;
///Field `BDMA1RST` writer - BDMA1 reset (DFSDM dedicated DMA) Set and reset by software.
pub use DCMI_PSSIRST_W as BDMA1RST_W;
impl R {
    ///Bit 0 - digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software.
    #[inline(always)]
    pub fn dcmi_pssirst(&self) -> DCMI_PSSIRST_R {
        DCMI_PSSIRST_R::new((self.bits & 1) != 0)
    }
    ///Bit 2 - HSEM block reset Set and reset by software.
    #[inline(always)]
    pub fn hsemrst(&self) -> HSEMRST_R {
        HSEMRST_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 6 - random number generator block reset Set and reset by software.
    #[inline(always)]
    pub fn rngrst(&self) -> RNGRST_R {
        RNGRST_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 9 - SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
    #[inline(always)]
    pub fn sdmmc2rst(&self) -> SDMMC2RST_R {
        SDMMC2RST_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 11 - BDMA1 reset (DFSDM dedicated DMA) Set and reset by software.
    #[inline(always)]
    pub fn bdma1rst(&self) -> BDMA1RST_R {
        BDMA1RST_R::new(((self.bits >> 11) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AHB2RSTR")
            .field("dcmi_pssirst", &self.dcmi_pssirst())
            .field("hsemrst", &self.hsemrst())
            .field("rngrst", &self.rngrst())
            .field("sdmmc2rst", &self.sdmmc2rst())
            .field("bdma1rst", &self.bdma1rst())
            .finish()
    }
}
impl W {
    ///Bit 0 - digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software.
    #[inline(always)]
    pub fn dcmi_pssirst(&mut self) -> DCMI_PSSIRST_W<AHB2RSTRrs> {
        DCMI_PSSIRST_W::new(self, 0)
    }
    ///Bit 2 - HSEM block reset Set and reset by software.
    #[inline(always)]
    pub fn hsemrst(&mut self) -> HSEMRST_W<AHB2RSTRrs> {
        HSEMRST_W::new(self, 2)
    }
    ///Bit 6 - random number generator block reset Set and reset by software.
    #[inline(always)]
    pub fn rngrst(&mut self) -> RNGRST_W<AHB2RSTRrs> {
        RNGRST_W::new(self, 6)
    }
    ///Bit 9 - SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
    #[inline(always)]
    pub fn sdmmc2rst(&mut self) -> SDMMC2RST_W<AHB2RSTRrs> {
        SDMMC2RST_W::new(self, 9)
    }
    ///Bit 11 - BDMA1 reset (DFSDM dedicated DMA) Set and reset by software.
    #[inline(always)]
    pub fn bdma1rst(&mut self) -> BDMA1RST_W<AHB2RSTRrs> {
        BDMA1RST_W::new(self, 11)
    }
}
/**

You can [`read`](crate::Reg::read) this register and get [`ahb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct AHB2RSTRrs;
impl crate::RegisterSpec for AHB2RSTRrs {
    type Ux = u32;
}
///`read()` method returns [`ahb2rstr::R`](R) reader structure
impl crate::Readable for AHB2RSTRrs {}
///`write(|w| ..)` method takes [`ahb2rstr::W`](W) writer structure
impl crate::Writable for AHB2RSTRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets AHB2RSTR to value 0
impl crate::Resettable for AHB2RSTRrs {}