stm32h7 0.16.0

///Register `CDCCIP1R` reader
pub type R = crate::R<CDCCIP1Rrs>;
///Register `CDCCIP1R` writer
pub type W = crate::W<CDCCIP1Rrs>;
/**SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SAI1SEL {
    ///0: pll1_q selected as peripheral clock
    Pll1Q = 0,
    ///1: pll2_p selected as peripheral clock
    Pll2P = 1,
    ///2: pll3_p selected as peripheral clock
    Pll3P = 2,
    ///3: I2S_CKIN selected as peripheral clock
    I2sCkin = 3,
    ///4: PER selected as peripheral clock
    Per = 4,
}
impl From<SAI1SEL> for u8 {
    #[inline(always)]
    fn from(variant: SAI1SEL) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for SAI1SEL {
    type Ux = u8;
}
impl crate::IsEnum for SAI1SEL {}
///Field `SAI1SEL` reader - SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
pub type SAI1SEL_R = crate::FieldReader<SAI1SEL>;
impl SAI1SEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<SAI1SEL> {
        match self.bits {
            0 => Some(SAI1SEL::Pll1Q),
            1 => Some(SAI1SEL::Pll2P),
            2 => Some(SAI1SEL::Pll3P),
            3 => Some(SAI1SEL::I2sCkin),
            4 => Some(SAI1SEL::Per),
            _ => None,
        }
    }
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == SAI1SEL::Pll1Q
    }
    ///pll2_p selected as peripheral clock
    #[inline(always)]
    pub fn is_pll2_p(&self) -> bool {
        *self == SAI1SEL::Pll2P
    }
    ///pll3_p selected as peripheral clock
    #[inline(always)]
    pub fn is_pll3_p(&self) -> bool {
        *self == SAI1SEL::Pll3P
    }
    ///I2S_CKIN selected as peripheral clock
    #[inline(always)]
    pub fn is_i2s_ckin(&self) -> bool {
        *self == SAI1SEL::I2sCkin
    }
    ///PER selected as peripheral clock
    #[inline(always)]
    pub fn is_per(&self) -> bool {
        *self == SAI1SEL::Per
    }
}
///Field `SAI1SEL` writer - SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
pub type SAI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SAI1SEL>;
impl<'a, REG> SAI1SEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut crate::W<REG> {
        self.variant(SAI1SEL::Pll1Q)
    }
    ///pll2_p selected as peripheral clock
    #[inline(always)]
    pub fn pll2_p(self) -> &'a mut crate::W<REG> {
        self.variant(SAI1SEL::Pll2P)
    }
    ///pll3_p selected as peripheral clock
    #[inline(always)]
    pub fn pll3_p(self) -> &'a mut crate::W<REG> {
        self.variant(SAI1SEL::Pll3P)
    }
    ///I2S_CKIN selected as peripheral clock
    #[inline(always)]
    pub fn i2s_ckin(self) -> &'a mut crate::W<REG> {
        self.variant(SAI1SEL::I2sCkin)
    }
    ///PER selected as peripheral clock
    #[inline(always)]
    pub fn per(self) -> &'a mut crate::W<REG> {
        self.variant(SAI1SEL::Per)
    }
}
/**SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SAI2ASEL {
    ///0: pll1_q selected as peripheral clock
    Pll1Q = 0,
    ///1: pll2_p selected as peripheral clock
    Pll2P = 1,
    ///2: pll3_p selected as peripheral clock
    Pll3P = 2,
    ///3: i2s_ckin selected as peripheral clock
    I2sCkin = 3,
    ///4: PER selected as peripheral clock
    Per = 4,
}
impl From<SAI2ASEL> for u8 {
    #[inline(always)]
    fn from(variant: SAI2ASEL) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for SAI2ASEL {
    type Ux = u8;
}
impl crate::IsEnum for SAI2ASEL {}
///Field `SAI2ASEL` reader - SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).
pub type SAI2ASEL_R = crate::FieldReader<SAI2ASEL>;
impl SAI2ASEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<SAI2ASEL> {
        match self.bits {
            0 => Some(SAI2ASEL::Pll1Q),
            1 => Some(SAI2ASEL::Pll2P),
            2 => Some(SAI2ASEL::Pll3P),
            3 => Some(SAI2ASEL::I2sCkin),
            4 => Some(SAI2ASEL::Per),
            _ => None,
        }
    }
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == SAI2ASEL::Pll1Q
    }
    ///pll2_p selected as peripheral clock
    #[inline(always)]
    pub fn is_pll2_p(&self) -> bool {
        *self == SAI2ASEL::Pll2P
    }
    ///pll3_p selected as peripheral clock
    #[inline(always)]
    pub fn is_pll3_p(&self) -> bool {
        *self == SAI2ASEL::Pll3P
    }
    ///i2s_ckin selected as peripheral clock
    #[inline(always)]
    pub fn is_i2s_ckin(&self) -> bool {
        *self == SAI2ASEL::I2sCkin
    }
    ///PER selected as peripheral clock
    #[inline(always)]
    pub fn is_per(&self) -> bool {
        *self == SAI2ASEL::Per
    }
}
///Field `SAI2ASEL` writer - SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).
pub type SAI2ASEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SAI2ASEL>;
impl<'a, REG> SAI2ASEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut crate::W<REG> {
        self.variant(SAI2ASEL::Pll1Q)
    }
    ///pll2_p selected as peripheral clock
    #[inline(always)]
    pub fn pll2_p(self) -> &'a mut crate::W<REG> {
        self.variant(SAI2ASEL::Pll2P)
    }
    ///pll3_p selected as peripheral clock
    #[inline(always)]
    pub fn pll3_p(self) -> &'a mut crate::W<REG> {
        self.variant(SAI2ASEL::Pll3P)
    }
    ///i2s_ckin selected as peripheral clock
    #[inline(always)]
    pub fn i2s_ckin(self) -> &'a mut crate::W<REG> {
        self.variant(SAI2ASEL::I2sCkin)
    }
    ///PER selected as peripheral clock
    #[inline(always)]
    pub fn per(self) -> &'a mut crate::W<REG> {
        self.variant(SAI2ASEL::Per)
    }
}
///Field `SPI123SEL` reader - SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
pub use SAI1SEL_R as SPI123SEL_R;
///Field `SPI123SEL` writer - SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
pub use SAI1SEL_W as SPI123SEL_W;
///Field `SAI2BSEL` reader - SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ).
pub use SAI2ASEL_R as SAI2BSEL_R;
///Field `SAI2BSEL` writer - SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ).
pub use SAI2ASEL_W as SAI2BSEL_W;
/**SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SPI45SEL {
    ///0: APB clock selected as peripheral clock
    Apb = 0,
    ///1: pll2_q selected as peripheral clock
    Pll2Q = 1,
    ///2: pll3_q selected as peripheral clock
    Pll3Q = 2,
    ///3: hsi_ker selected as peripheral clock
    HsiKer = 3,
    ///4: csi_ker selected as peripheral clock
    CsiKer = 4,
    ///5: HSE selected as peripheral clock
    Hse = 5,
}
impl From<SPI45SEL> for u8 {
    #[inline(always)]
    fn from(variant: SPI45SEL) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for SPI45SEL {
    type Ux = u8;
}
impl crate::IsEnum for SPI45SEL {}
///Field `SPI45SEL` reader - SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled
pub type SPI45SEL_R = crate::FieldReader<SPI45SEL>;
impl SPI45SEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<SPI45SEL> {
        match self.bits {
            0 => Some(SPI45SEL::Apb),
            1 => Some(SPI45SEL::Pll2Q),
            2 => Some(SPI45SEL::Pll3Q),
            3 => Some(SPI45SEL::HsiKer),
            4 => Some(SPI45SEL::CsiKer),
            5 => Some(SPI45SEL::Hse),
            _ => None,
        }
    }
    ///APB clock selected as peripheral clock
    #[inline(always)]
    pub fn is_apb(&self) -> bool {
        *self == SPI45SEL::Apb
    }
    ///pll2_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll2_q(&self) -> bool {
        *self == SPI45SEL::Pll2Q
    }
    ///pll3_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll3_q(&self) -> bool {
        *self == SPI45SEL::Pll3Q
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SPI45SEL::HsiKer
    }
    ///csi_ker selected as peripheral clock
    #[inline(always)]
    pub fn is_csi_ker(&self) -> bool {
        *self == SPI45SEL::CsiKer
    }
    ///HSE selected as peripheral clock
    #[inline(always)]
    pub fn is_hse(&self) -> bool {
        *self == SPI45SEL::Hse
    }
}
///Field `SPI45SEL` writer - SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled
pub type SPI45SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SPI45SEL>;
impl<'a, REG> SPI45SEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///APB clock selected as peripheral clock
    #[inline(always)]
    pub fn apb(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::Apb)
    }
    ///pll2_q selected as peripheral clock
    #[inline(always)]
    pub fn pll2_q(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::Pll2Q)
    }
    ///pll3_q selected as peripheral clock
    #[inline(always)]
    pub fn pll3_q(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::Pll3Q)
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::HsiKer)
    }
    ///csi_ker selected as peripheral clock
    #[inline(always)]
    pub fn csi_ker(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::CsiKer)
    }
    ///HSE selected as peripheral clock
    #[inline(always)]
    pub fn hse(self) -> &'a mut crate::W<REG> {
        self.variant(SPI45SEL::Hse)
    }
}
/**SPDIFRX kernel clock source selection

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SPDIFRXSEL {
    ///0: pll1_q selected as peripheral clock
    Pll1Q = 0,
    ///1: pll2_r selected as peripheral clock
    Pll2R = 1,
    ///2: pll3_r selected as peripheral clock
    Pll3R = 2,
    ///3: hsi_ker selected as peripheral clock
    HsiKer = 3,
}
impl From<SPDIFRXSEL> for u8 {
    #[inline(always)]
    fn from(variant: SPDIFRXSEL) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for SPDIFRXSEL {
    type Ux = u8;
}
impl crate::IsEnum for SPDIFRXSEL {}
///Field `SPDIFRXSEL` reader - SPDIFRX kernel clock source selection
pub type SPDIFRXSEL_R = crate::FieldReader<SPDIFRXSEL>;
impl SPDIFRXSEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> SPDIFRXSEL {
        match self.bits {
            0 => SPDIFRXSEL::Pll1Q,
            1 => SPDIFRXSEL::Pll2R,
            2 => SPDIFRXSEL::Pll3R,
            3 => SPDIFRXSEL::HsiKer,
            _ => unreachable!(),
        }
    }
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == SPDIFRXSEL::Pll1Q
    }
    ///pll2_r selected as peripheral clock
    #[inline(always)]
    pub fn is_pll2_r(&self) -> bool {
        *self == SPDIFRXSEL::Pll2R
    }
    ///pll3_r selected as peripheral clock
    #[inline(always)]
    pub fn is_pll3_r(&self) -> bool {
        *self == SPDIFRXSEL::Pll3R
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SPDIFRXSEL::HsiKer
    }
}
///Field `SPDIFRXSEL` writer - SPDIFRX kernel clock source selection
pub type SPDIFRXSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPDIFRXSEL, crate::Safe>;
impl<'a, REG> SPDIFRXSEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut crate::W<REG> {
        self.variant(SPDIFRXSEL::Pll1Q)
    }
    ///pll2_r selected as peripheral clock
    #[inline(always)]
    pub fn pll2_r(self) -> &'a mut crate::W<REG> {
        self.variant(SPDIFRXSEL::Pll2R)
    }
    ///pll3_r selected as peripheral clock
    #[inline(always)]
    pub fn pll3_r(self) -> &'a mut crate::W<REG> {
        self.variant(SPDIFRXSEL::Pll3R)
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut crate::W<REG> {
        self.variant(SPDIFRXSEL::HsiKer)
    }
}
/**DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DFSDM1SEL {
    ///0: rcc_pclk2 selected as peripheral clock
    RccPclk2 = 0,
    ///1: System clock selected as peripheral clock
    Sys = 1,
}
impl From<DFSDM1SEL> for bool {
    #[inline(always)]
    fn from(variant: DFSDM1SEL) -> Self {
        variant as u8 != 0
    }
}
///Field `DFSDM1SEL` reader - DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).
pub type DFSDM1SEL_R = crate::BitReader<DFSDM1SEL>;
impl DFSDM1SEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> DFSDM1SEL {
        match self.bits {
            false => DFSDM1SEL::RccPclk2,
            true => DFSDM1SEL::Sys,
        }
    }
    ///rcc_pclk2 selected as peripheral clock
    #[inline(always)]
    pub fn is_rcc_pclk2(&self) -> bool {
        *self == DFSDM1SEL::RccPclk2
    }
    ///System clock selected as peripheral clock
    #[inline(always)]
    pub fn is_sys(&self) -> bool {
        *self == DFSDM1SEL::Sys
    }
}
///Field `DFSDM1SEL` writer - DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).
pub type DFSDM1SEL_W<'a, REG> = crate::BitWriter<'a, REG, DFSDM1SEL>;
impl<'a, REG> DFSDM1SEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///rcc_pclk2 selected as peripheral clock
    #[inline(always)]
    pub fn rcc_pclk2(self) -> &'a mut crate::W<REG> {
        self.variant(DFSDM1SEL::RccPclk2)
    }
    ///System clock selected as peripheral clock
    #[inline(always)]
    pub fn sys(self) -> &'a mut crate::W<REG> {
        self.variant(DFSDM1SEL::Sys)
    }
}
/**FDCAN kernel clock source selection Set and reset by software.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum FDCANSEL {
    ///0: HSE selected as peripheral clock
    Hse = 0,
    ///1: pll1_q selected as peripheral clock
    Pll1Q = 1,
    ///2: pll2_q selected as peripheral clock
    Pll2Q = 2,
}
impl From<FDCANSEL> for u8 {
    #[inline(always)]
    fn from(variant: FDCANSEL) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for FDCANSEL {
    type Ux = u8;
}
impl crate::IsEnum for FDCANSEL {}
///Field `FDCANSEL` reader - FDCAN kernel clock source selection Set and reset by software.
pub type FDCANSEL_R = crate::FieldReader<FDCANSEL>;
impl FDCANSEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<FDCANSEL> {
        match self.bits {
            0 => Some(FDCANSEL::Hse),
            1 => Some(FDCANSEL::Pll1Q),
            2 => Some(FDCANSEL::Pll2Q),
            _ => None,
        }
    }
    ///HSE selected as peripheral clock
    #[inline(always)]
    pub fn is_hse(&self) -> bool {
        *self == FDCANSEL::Hse
    }
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll1_q(&self) -> bool {
        *self == FDCANSEL::Pll1Q
    }
    ///pll2_q selected as peripheral clock
    #[inline(always)]
    pub fn is_pll2_q(&self) -> bool {
        *self == FDCANSEL::Pll2Q
    }
}
///Field `FDCANSEL` writer - FDCAN kernel clock source selection Set and reset by software.
pub type FDCANSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FDCANSEL>;
impl<'a, REG> FDCANSEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///HSE selected as peripheral clock
    #[inline(always)]
    pub fn hse(self) -> &'a mut crate::W<REG> {
        self.variant(FDCANSEL::Hse)
    }
    ///pll1_q selected as peripheral clock
    #[inline(always)]
    pub fn pll1_q(self) -> &'a mut crate::W<REG> {
        self.variant(FDCANSEL::Pll1Q)
    }
    ///pll2_q selected as peripheral clock
    #[inline(always)]
    pub fn pll2_q(self) -> &'a mut crate::W<REG> {
        self.variant(FDCANSEL::Pll2Q)
    }
}
/**SWPMI kernel clock source selection Set and reset by software.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SWPMISEL {
    ///0: pclk selected as peripheral clock
    Pclk = 0,
    ///1: hsi_ker selected as peripheral clock
    HsiKer = 1,
}
impl From<SWPMISEL> for bool {
    #[inline(always)]
    fn from(variant: SWPMISEL) -> Self {
        variant as u8 != 0
    }
}
///Field `SWPMISEL` reader - SWPMI kernel clock source selection Set and reset by software.
pub type SWPMISEL_R = crate::BitReader<SWPMISEL>;
impl SWPMISEL_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> SWPMISEL {
        match self.bits {
            false => SWPMISEL::Pclk,
            true => SWPMISEL::HsiKer,
        }
    }
    ///pclk selected as peripheral clock
    #[inline(always)]
    pub fn is_pclk(&self) -> bool {
        *self == SWPMISEL::Pclk
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn is_hsi_ker(&self) -> bool {
        *self == SWPMISEL::HsiKer
    }
}
///Field `SWPMISEL` writer - SWPMI kernel clock source selection Set and reset by software.
pub type SWPMISEL_W<'a, REG> = crate::BitWriter<'a, REG, SWPMISEL>;
impl<'a, REG> SWPMISEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///pclk selected as peripheral clock
    #[inline(always)]
    pub fn pclk(self) -> &'a mut crate::W<REG> {
        self.variant(SWPMISEL::Pclk)
    }
    ///hsi_ker selected as peripheral clock
    #[inline(always)]
    pub fn hsi_ker(self) -> &'a mut crate::W<REG> {
        self.variant(SWPMISEL::HsiKer)
    }
}
impl R {
    ///Bits 0:2 - SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
    #[inline(always)]
    pub fn sai1sel(&self) -> SAI1SEL_R {
        SAI1SEL_R::new((self.bits & 7) as u8)
    }
    ///Bits 6:8 - SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).
    #[inline(always)]
    pub fn sai2asel(&self) -> SAI2ASEL_R {
        SAI2ASEL_R::new(((self.bits >> 6) & 7) as u8)
    }
    ///Bits 9:11 - SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ).
    #[inline(always)]
    pub fn sai2bsel(&self) -> SAI2BSEL_R {
        SAI2BSEL_R::new(((self.bits >> 9) & 7) as u8)
    }
    ///Bits 12:14 - SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
    #[inline(always)]
    pub fn spi123sel(&self) -> SPI123SEL_R {
        SPI123SEL_R::new(((self.bits >> 12) & 7) as u8)
    }
    ///Bits 16:18 - SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled
    #[inline(always)]
    pub fn spi45sel(&self) -> SPI45SEL_R {
        SPI45SEL_R::new(((self.bits >> 16) & 7) as u8)
    }
    ///Bits 20:21 - SPDIFRX kernel clock source selection
    #[inline(always)]
    pub fn spdifrxsel(&self) -> SPDIFRXSEL_R {
        SPDIFRXSEL_R::new(((self.bits >> 20) & 3) as u8)
    }
    ///Bit 24 - DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).
    #[inline(always)]
    pub fn dfsdm1sel(&self) -> DFSDM1SEL_R {
        DFSDM1SEL_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bits 28:29 - FDCAN kernel clock source selection Set and reset by software.
    #[inline(always)]
    pub fn fdcansel(&self) -> FDCANSEL_R {
        FDCANSEL_R::new(((self.bits >> 28) & 3) as u8)
    }
    ///Bit 31 - SWPMI kernel clock source selection Set and reset by software.
    #[inline(always)]
    pub fn swpmisel(&self) -> SWPMISEL_R {
        SWPMISEL_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CDCCIP1R")
            .field("sai1sel", &self.sai1sel())
            .field("sai2asel", &self.sai2asel())
            .field("sai2bsel", &self.sai2bsel())
            .field("spi123sel", &self.spi123sel())
            .field("spi45sel", &self.spi45sel())
            .field("spdifrxsel", &self.spdifrxsel())
            .field("dfsdm1sel", &self.dfsdm1sel())
            .field("fdcansel", &self.fdcansel())
            .field("swpmisel", &self.swpmisel())
            .finish()
    }
}
impl W {
    ///Bits 0:2 - SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
    #[inline(always)]
    pub fn sai1sel(&mut self) -> SAI1SEL_W<CDCCIP1Rrs> {
        SAI1SEL_W::new(self, 0)
    }
    ///Bits 6:8 - SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).
    #[inline(always)]
    pub fn sai2asel(&mut self) -> SAI2ASEL_W<CDCCIP1Rrs> {
        SAI2ASEL_W::new(self, 6)
    }
    ///Bits 9:11 - SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ).
    #[inline(always)]
    pub fn sai2bsel(&mut self) -> SAI2BSEL_W<CDCCIP1Rrs> {
        SAI2BSEL_W::new(self, 9)
    }
    ///Bits 12:14 - SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.
    #[inline(always)]
    pub fn spi123sel(&mut self) -> SPI123SEL_W<CDCCIP1Rrs> {
        SPI123SEL_W::new(self, 12)
    }
    ///Bits 16:18 - SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled
    #[inline(always)]
    pub fn spi45sel(&mut self) -> SPI45SEL_W<CDCCIP1Rrs> {
        SPI45SEL_W::new(self, 16)
    }
    ///Bits 20:21 - SPDIFRX kernel clock source selection
    #[inline(always)]
    pub fn spdifrxsel(&mut self) -> SPDIFRXSEL_W<CDCCIP1Rrs> {
        SPDIFRXSEL_W::new(self, 20)
    }
    ///Bit 24 - DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).
    #[inline(always)]
    pub fn dfsdm1sel(&mut self) -> DFSDM1SEL_W<CDCCIP1Rrs> {
        DFSDM1SEL_W::new(self, 24)
    }
    ///Bits 28:29 - FDCAN kernel clock source selection Set and reset by software.
    #[inline(always)]
    pub fn fdcansel(&mut self) -> FDCANSEL_W<CDCCIP1Rrs> {
        FDCANSEL_W::new(self, 28)
    }
    ///Bit 31 - SWPMI kernel clock source selection Set and reset by software.
    #[inline(always)]
    pub fn swpmisel(&mut self) -> SWPMISEL_W<CDCCIP1Rrs> {
        SWPMISEL_W::new(self, 31)
    }
}
/**RCC CPU domain kernel clock configuration register

You can [`read`](crate::Reg::read) this register and get [`cdccip1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cdccip1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CDCCIP1Rrs;
impl crate::RegisterSpec for CDCCIP1Rrs {
    type Ux = u32;
}
///`read()` method returns [`cdccip1r::R`](R) reader structure
impl crate::Readable for CDCCIP1Rrs {}
///`write(|w| ..)` method takes [`cdccip1r::W`](W) writer structure
impl crate::Writable for CDCCIP1Rrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CDCCIP1R to value 0
impl crate::Resettable for CDCCIP1Rrs {}