stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `TSCV` reader
pub type R = crate::R<TSCVrs>;
///Register `TSCV` writer
pub type W = crate::W<TSCVrs>;
///Field `TSC` reader - Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\[TSS\] = 01, the timestamp counter is incremented in multiples of CAN bit times \[1..16\] depending on the configuration of TSCC\[TCP\]. A wrap around sets interrupt flag IR\[TSW\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact.
pub type TSC_R = crate::FieldReader<u16>;
///Field `TSC` writer - Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\[TSS\] = 01, the timestamp counter is incremented in multiples of CAN bit times \[1..16\] depending on the configuration of TSCC\[TCP\]. A wrap around sets interrupt flag IR\[TSW\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact.
pub type TSC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
    ///Bits 0:15 - Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\[TSS\] = 01, the timestamp counter is incremented in multiples of CAN bit times \[1..16\] depending on the configuration of TSCC\[TCP\]. A wrap around sets interrupt flag IR\[TSW\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact.
    #[inline(always)]
    pub fn tsc(&self) -> TSC_R {
        TSC_R::new((self.bits & 0xffff) as u16)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TSCV").field("tsc", &self.tsc()).finish()
    }
}
impl W {
    ///Bits 0:15 - Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC\[TSS\] = 01, the timestamp counter is incremented in multiples of CAN bit times \[1..16\] depending on the configuration of TSCC\[TCP\]. A wrap around sets interrupt flag IR\[TSW\]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact.
    #[inline(always)]
    pub fn tsc(&mut self) -> TSC_W<TSCVrs> {
        TSC_W::new(self, 0)
    }
}
/**FDCAN Timestamp Counter Value Register

You can [`read`](crate::Reg::read) this register and get [`tscv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tscv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct TSCVrs;
impl crate::RegisterSpec for TSCVrs {
    type Ux = u32;
}
///`read()` method returns [`tscv::R`](R) reader structure
impl crate::Readable for TSCVrs {}
///`write(|w| ..)` method takes [`tscv::W`](W) writer structure
impl crate::Writable for TSCVrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets TSCV to value 0
impl crate::Resettable for TSCVrs {}