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#[repr(C)]
#[derive(Debug)]
///Register block
pub struct RegisterBlock {
moder: MODER,
otyper: OTYPER,
ospeedr: OSPEEDR,
pupdr: PUPDR,
idr: IDR,
odr: ODR,
bsrr: BSRR,
lckr: LCKR,
afrl: AFRL,
_reserved9: [u8; 0x04],
brr: BRR,
hslvr: HSLVR,
seccfgr: SECCFGR,
}
impl RegisterBlock {
///0x00 - GPIO port mode register
#[inline(always)]
pub const fn moder(&self) -> &MODER {
&self.moder
}
///0x04 - GPIO port output type register
#[inline(always)]
pub const fn otyper(&self) -> &OTYPER {
&self.otyper
}
///0x08 - GPIO port output speed register
#[inline(always)]
pub const fn ospeedr(&self) -> &OSPEEDR {
&self.ospeedr
}
///0x0c - GPIO port pull-up/pull-down register
#[inline(always)]
pub const fn pupdr(&self) -> &PUPDR {
&self.pupdr
}
///0x10 - GPIO port input data register
#[inline(always)]
pub const fn idr(&self) -> &IDR {
&self.idr
}
///0x14 - GPIO port output data register
#[inline(always)]
pub const fn odr(&self) -> &ODR {
&self.odr
}
///0x18 - GPIO port bit set/reset register
#[inline(always)]
pub const fn bsrr(&self) -> &BSRR {
&self.bsrr
}
///0x1c - GPIO port configuration lock register
#[inline(always)]
pub const fn lckr(&self) -> &LCKR {
&self.lckr
}
///0x20 - GPIO alternate function low register
#[inline(always)]
pub const fn afrl(&self) -> &AFRL {
&self.afrl
}
///0x28 - GPIO port bit reset register
#[inline(always)]
pub const fn brr(&self) -> &BRR {
&self.brr
}
///0x2c - GPIO high-speed low-voltage register
#[inline(always)]
pub const fn hslvr(&self) -> &HSLVR {
&self.hslvr
}
///0x30 - GPIO secure configuration register
#[inline(always)]
pub const fn seccfgr(&self) -> &SECCFGR {
&self.seccfgr
}
}
/**MODER (rw) register accessor: GPIO port mode register
You can [`read`](crate::Reg::read) this register and get [`moder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`moder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H563.html#GPIOI:MODER)
For information about available fields see [`mod@moder`] module*/
pub type MODER = crate::Reg<moder::MODERrs>;
///GPIO port mode register
pub mod moder;
pub use crate::stm32h563::gpioa::otyper;
pub use crate::stm32h563::gpioa::OTYPER;
/**OSPEEDR (rw) register accessor: GPIO port output speed register
You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H563.html#GPIOI:OSPEEDR)
For information about available fields see [`mod@ospeedr`] module*/
pub type OSPEEDR = crate::Reg<ospeedr::OSPEEDRrs>;
///GPIO port output speed register
pub mod ospeedr;
/**PUPDR (rw) register accessor: GPIO port pull-up/pull-down register
You can [`read`](crate::Reg::read) this register and get [`pupdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pupdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H563.html#GPIOI:PUPDR)
For information about available fields see [`mod@pupdr`] module*/
pub type PUPDR = crate::Reg<pupdr::PUPDRrs>;
///GPIO port pull-up/pull-down register
pub mod pupdr;
pub use crate::stm32h563::gpioa::afrl;
pub use crate::stm32h563::gpioa::brr;
pub use crate::stm32h563::gpioa::bsrr;
pub use crate::stm32h563::gpioa::hslvr;
pub use crate::stm32h563::gpioa::idr;
pub use crate::stm32h563::gpioa::lckr;
pub use crate::stm32h563::gpioa::odr;
pub use crate::stm32h563::gpioa::AFRL;
pub use crate::stm32h563::gpioa::BRR;
pub use crate::stm32h563::gpioa::BSRR;
pub use crate::stm32h563::gpioa::HSLVR;
pub use crate::stm32h563::gpioa::IDR;
pub use crate::stm32h563::gpioa::LCKR;
pub use crate::stm32h563::gpioa::ODR;
/**SECCFGR (rw) register accessor: GPIO secure configuration register
You can [`read`](crate::Reg::read) this register and get [`seccfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H563.html#GPIOI:SECCFGR)
For information about available fields see [`mod@seccfgr`] module*/
pub type SECCFGR = crate::Reg<seccfgr::SECCFGRrs>;
///GPIO secure configuration register
pub mod seccfgr;