#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SMPR2 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `SMP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMP0R {
#[doc = "1.5 ADC clock cycles"]
CYCLES1_5,
#[doc = "7.5 ADC clock cycles"]
CYCLES7_5,
#[doc = "13.5 ADC clock cycles"]
CYCLES13_5,
#[doc = "28.5 ADC clock cycles"]
CYCLES28_5,
#[doc = "41.5 ADC clock cycles"]
CYCLES41_5,
#[doc = "55.5 ADC clock cycles"]
CYCLES55_5,
#[doc = "71.5 ADC clock cycles"]
CYCLES71_5,
#[doc = "239.5 ADC clock cycles"]
CYCLES239_5,
}
impl SMP0R {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SMP0R::CYCLES1_5 => 0,
SMP0R::CYCLES7_5 => 0x01,
SMP0R::CYCLES13_5 => 0x02,
SMP0R::CYCLES28_5 => 0x03,
SMP0R::CYCLES41_5 => 0x04,
SMP0R::CYCLES55_5 => 0x05,
SMP0R::CYCLES71_5 => 0x06,
SMP0R::CYCLES239_5 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SMP0R {
match value {
0 => SMP0R::CYCLES1_5,
1 => SMP0R::CYCLES7_5,
2 => SMP0R::CYCLES13_5,
3 => SMP0R::CYCLES28_5,
4 => SMP0R::CYCLES41_5,
5 => SMP0R::CYCLES55_5,
6 => SMP0R::CYCLES71_5,
7 => SMP0R::CYCLES239_5,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CYCLES1_5`"]
#[inline(always)]
pub fn is_cycles1_5(&self) -> bool {
*self == SMP0R::CYCLES1_5
}
#[doc = "Checks if the value of the field is `CYCLES7_5`"]
#[inline(always)]
pub fn is_cycles7_5(&self) -> bool {
*self == SMP0R::CYCLES7_5
}
#[doc = "Checks if the value of the field is `CYCLES13_5`"]
#[inline(always)]
pub fn is_cycles13_5(&self) -> bool {
*self == SMP0R::CYCLES13_5
}
#[doc = "Checks if the value of the field is `CYCLES28_5`"]
#[inline(always)]
pub fn is_cycles28_5(&self) -> bool {
*self == SMP0R::CYCLES28_5
}
#[doc = "Checks if the value of the field is `CYCLES41_5`"]
#[inline(always)]
pub fn is_cycles41_5(&self) -> bool {
*self == SMP0R::CYCLES41_5
}
#[doc = "Checks if the value of the field is `CYCLES55_5`"]
#[inline(always)]
pub fn is_cycles55_5(&self) -> bool {
*self == SMP0R::CYCLES55_5
}
#[doc = "Checks if the value of the field is `CYCLES71_5`"]
#[inline(always)]
pub fn is_cycles71_5(&self) -> bool {
*self == SMP0R::CYCLES71_5
}
#[doc = "Checks if the value of the field is `CYCLES239_5`"]
#[inline(always)]
pub fn is_cycles239_5(&self) -> bool {
*self == SMP0R::CYCLES239_5
}
}
#[doc = "Values that can be written to the field `SMP0`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMP0W {
#[doc = "1.5 ADC clock cycles"]
CYCLES1_5,
#[doc = "7.5 ADC clock cycles"]
CYCLES7_5,
#[doc = "13.5 ADC clock cycles"]
CYCLES13_5,
#[doc = "28.5 ADC clock cycles"]
CYCLES28_5,
#[doc = "41.5 ADC clock cycles"]
CYCLES41_5,
#[doc = "55.5 ADC clock cycles"]
CYCLES55_5,
#[doc = "71.5 ADC clock cycles"]
CYCLES71_5,
#[doc = "239.5 ADC clock cycles"]
CYCLES239_5,
}
impl SMP0W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SMP0W::CYCLES1_5 => 0,
SMP0W::CYCLES7_5 => 1,
SMP0W::CYCLES13_5 => 2,
SMP0W::CYCLES28_5 => 3,
SMP0W::CYCLES41_5 => 4,
SMP0W::CYCLES55_5 => 5,
SMP0W::CYCLES71_5 => 6,
SMP0W::CYCLES239_5 => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _SMP0W<'a> {
w: &'a mut W,
}
impl<'a> _SMP0W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP0W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 0);
self.w.bits |= ((value as u32) & 0x07) << 0;
self.w
}
}
#[doc = "Possible values of the field `SMP1`"]
pub type SMP1R = SMP0R;
#[doc = "Values that can be written to the field `SMP1`"]
pub type SMP1W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP1W<'a> {
w: &'a mut W,
}
impl<'a> _SMP1W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 3);
self.w.bits |= ((value as u32) & 0x07) << 3;
self.w
}
}
#[doc = "Possible values of the field `SMP2`"]
pub type SMP2R = SMP0R;
#[doc = "Values that can be written to the field `SMP2`"]
pub type SMP2W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP2W<'a> {
w: &'a mut W,
}
impl<'a> _SMP2W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 6);
self.w.bits |= ((value as u32) & 0x07) << 6;
self.w
}
}
#[doc = "Possible values of the field `SMP3`"]
pub type SMP3R = SMP0R;
#[doc = "Values that can be written to the field `SMP3`"]
pub type SMP3W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP3W<'a> {
w: &'a mut W,
}
impl<'a> _SMP3W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP3W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 9);
self.w.bits |= ((value as u32) & 0x07) << 9;
self.w
}
}
#[doc = "Possible values of the field `SMP4`"]
pub type SMP4R = SMP0R;
#[doc = "Values that can be written to the field `SMP4`"]
pub type SMP4W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP4W<'a> {
w: &'a mut W,
}
impl<'a> _SMP4W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP4W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 12);
self.w.bits |= ((value as u32) & 0x07) << 12;
self.w
}
}
#[doc = "Possible values of the field `SMP5`"]
pub type SMP5R = SMP0R;
#[doc = "Values that can be written to the field `SMP5`"]
pub type SMP5W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP5W<'a> {
w: &'a mut W,
}
impl<'a> _SMP5W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP5W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 15);
self.w.bits |= ((value as u32) & 0x07) << 15;
self.w
}
}
#[doc = "Possible values of the field `SMP6`"]
pub type SMP6R = SMP0R;
#[doc = "Values that can be written to the field `SMP6`"]
pub type SMP6W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP6W<'a> {
w: &'a mut W,
}
impl<'a> _SMP6W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP6W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 18);
self.w.bits |= ((value as u32) & 0x07) << 18;
self.w
}
}
#[doc = "Possible values of the field `SMP7`"]
pub type SMP7R = SMP0R;
#[doc = "Values that can be written to the field `SMP7`"]
pub type SMP7W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP7W<'a> {
w: &'a mut W,
}
impl<'a> _SMP7W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP7W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 21);
self.w.bits |= ((value as u32) & 0x07) << 21;
self.w
}
}
#[doc = "Possible values of the field `SMP8`"]
pub type SMP8R = SMP0R;
#[doc = "Values that can be written to the field `SMP8`"]
pub type SMP8W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP8W<'a> {
w: &'a mut W,
}
impl<'a> _SMP8W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP8W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 24);
self.w.bits |= ((value as u32) & 0x07) << 24;
self.w
}
}
#[doc = "Possible values of the field `SMP9`"]
pub type SMP9R = SMP0R;
#[doc = "Values that can be written to the field `SMP9`"]
pub type SMP9W = SMP0W;
#[doc = r"Proxy"]
pub struct _SMP9W<'a> {
w: &'a mut W,
}
impl<'a> _SMP9W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP9W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP0W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 27);
self.w.bits |= ((value as u32) & 0x07) << 27;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Channel 0 sample time selection"]
#[inline(always)]
pub fn smp0(&self) -> SMP0R {
SMP0R::_from(((self.bits >> 0) & 0x07) as u8)
}
#[doc = "Bits 3:5 - Channel 1 sample time selection"]
#[inline(always)]
pub fn smp1(&self) -> SMP1R {
SMP1R::_from(((self.bits >> 3) & 0x07) as u8)
}
#[doc = "Bits 6:8 - Channel 2 sample time selection"]
#[inline(always)]
pub fn smp2(&self) -> SMP2R {
SMP2R::_from(((self.bits >> 6) & 0x07) as u8)
}
#[doc = "Bits 9:11 - Channel 3 sample time selection"]
#[inline(always)]
pub fn smp3(&self) -> SMP3R {
SMP3R::_from(((self.bits >> 9) & 0x07) as u8)
}
#[doc = "Bits 12:14 - Channel 4 sample time selection"]
#[inline(always)]
pub fn smp4(&self) -> SMP4R {
SMP4R::_from(((self.bits >> 12) & 0x07) as u8)
}
#[doc = "Bits 15:17 - Channel 5 sample time selection"]
#[inline(always)]
pub fn smp5(&self) -> SMP5R {
SMP5R::_from(((self.bits >> 15) & 0x07) as u8)
}
#[doc = "Bits 18:20 - Channel 6 sample time selection"]
#[inline(always)]
pub fn smp6(&self) -> SMP6R {
SMP6R::_from(((self.bits >> 18) & 0x07) as u8)
}
#[doc = "Bits 21:23 - Channel 7 sample time selection"]
#[inline(always)]
pub fn smp7(&self) -> SMP7R {
SMP7R::_from(((self.bits >> 21) & 0x07) as u8)
}
#[doc = "Bits 24:26 - Channel 8 sample time selection"]
#[inline(always)]
pub fn smp8(&self) -> SMP8R {
SMP8R::_from(((self.bits >> 24) & 0x07) as u8)
}
#[doc = "Bits 27:29 - Channel 9 sample time selection"]
#[inline(always)]
pub fn smp9(&self) -> SMP9R {
SMP9R::_from(((self.bits >> 27) & 0x07) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Channel 0 sample time selection"]
#[inline(always)]
pub fn smp0(&mut self) -> _SMP0W {
_SMP0W { w: self }
}
#[doc = "Bits 3:5 - Channel 1 sample time selection"]
#[inline(always)]
pub fn smp1(&mut self) -> _SMP1W {
_SMP1W { w: self }
}
#[doc = "Bits 6:8 - Channel 2 sample time selection"]
#[inline(always)]
pub fn smp2(&mut self) -> _SMP2W {
_SMP2W { w: self }
}
#[doc = "Bits 9:11 - Channel 3 sample time selection"]
#[inline(always)]
pub fn smp3(&mut self) -> _SMP3W {
_SMP3W { w: self }
}
#[doc = "Bits 12:14 - Channel 4 sample time selection"]
#[inline(always)]
pub fn smp4(&mut self) -> _SMP4W {
_SMP4W { w: self }
}
#[doc = "Bits 15:17 - Channel 5 sample time selection"]
#[inline(always)]
pub fn smp5(&mut self) -> _SMP5W {
_SMP5W { w: self }
}
#[doc = "Bits 18:20 - Channel 6 sample time selection"]
#[inline(always)]
pub fn smp6(&mut self) -> _SMP6W {
_SMP6W { w: self }
}
#[doc = "Bits 21:23 - Channel 7 sample time selection"]
#[inline(always)]
pub fn smp7(&mut self) -> _SMP7W {
_SMP7W { w: self }
}
#[doc = "Bits 24:26 - Channel 8 sample time selection"]
#[inline(always)]
pub fn smp8(&mut self) -> _SMP8W {
_SMP8W { w: self }
}
#[doc = "Bits 27:29 - Channel 9 sample time selection"]
#[inline(always)]
pub fn smp9(&mut self) -> _SMP9W {
_SMP9W { w: self }
}
}