#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR2 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `TSVREFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TSVREFER {
#[doc = "Temperature sensor and V_REFINT channel disabled"]
DISABLED,
#[doc = "Temperature sensor and V_REFINT channel enabled"]
ENABLED,
}
impl TSVREFER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
TSVREFER::DISABLED => false,
TSVREFER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> TSVREFER {
match value {
false => TSVREFER::DISABLED,
true => TSVREFER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TSVREFER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TSVREFER::ENABLED
}
}
#[doc = "Values that can be written to the field `TSVREFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TSVREFEW {
#[doc = "Temperature sensor and V_REFINT channel disabled"]
DISABLED,
#[doc = "Temperature sensor and V_REFINT channel enabled"]
ENABLED,
}
impl TSVREFEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
TSVREFEW::DISABLED => false,
TSVREFEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _TSVREFEW<'a> {
w: &'a mut W,
}
impl<'a> _TSVREFEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TSVREFEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Temperature sensor and V_REFINT channel disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(TSVREFEW::DISABLED)
}
#[doc = "Temperature sensor and V_REFINT channel enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(TSVREFEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 23);
self.w.bits |= ((value as u32) & 0x01) << 23;
self.w
}
}
#[doc = "Possible values of the field `SWSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWSTARTR {
#[doc = "Reset state"]
STARTED,
#[doc = "Starting conversion of regular channels"]
NOTSTARTED,
}
impl SWSTARTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SWSTARTR::STARTED => false,
SWSTARTR::NOTSTARTED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SWSTARTR {
match value {
false => SWSTARTR::STARTED,
true => SWSTARTR::NOTSTARTED,
}
}
#[doc = "Checks if the value of the field is `STARTED`"]
#[inline(always)]
pub fn is_started(&self) -> bool {
*self == SWSTARTR::STARTED
}
#[doc = "Checks if the value of the field is `NOTSTARTED`"]
#[inline(always)]
pub fn is_not_started(&self) -> bool {
*self == SWSTARTR::NOTSTARTED
}
}
#[doc = "Values that can be written to the field `SWSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWSTARTW {
#[doc = "Start conversion of regular channels"]
START,
}
impl SWSTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SWSTARTW::START => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SWSTARTW<'a> {
w: &'a mut W,
}
impl<'a> _SWSTARTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SWSTARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Start conversion of regular channels"]
#[inline(always)]
pub fn start(self) -> &'a mut W {
self.variant(SWSTARTW::START)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = "Possible values of the field `JSWSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JSWSTARTR {
#[doc = "Reset state"]
STARTED,
#[doc = "Starting conversion of injected channels"]
NOTSTARTED,
}
impl JSWSTARTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
JSWSTARTR::STARTED => false,
JSWSTARTR::NOTSTARTED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> JSWSTARTR {
match value {
false => JSWSTARTR::STARTED,
true => JSWSTARTR::NOTSTARTED,
}
}
#[doc = "Checks if the value of the field is `STARTED`"]
#[inline(always)]
pub fn is_started(&self) -> bool {
*self == JSWSTARTR::STARTED
}
#[doc = "Checks if the value of the field is `NOTSTARTED`"]
#[inline(always)]
pub fn is_not_started(&self) -> bool {
*self == JSWSTARTR::NOTSTARTED
}
}
#[doc = "Values that can be written to the field `JSWSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JSWSTARTW {
#[doc = "Start conversion of injected channels"]
START,
}
impl JSWSTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
JSWSTARTW::START => true,
}
}
}
#[doc = r"Proxy"]
pub struct _JSWSTARTW<'a> {
w: &'a mut W,
}
impl<'a> _JSWSTARTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: JSWSTARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Start conversion of injected channels"]
#[inline(always)]
pub fn start(self) -> &'a mut W {
self.variant(JSWSTARTW::START)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 21);
self.w.bits |= ((value as u32) & 0x01) << 21;
self.w
}
}
#[doc = "Possible values of the field `EXTTRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTTRIGR {
#[doc = "Conversion on external event disabled"]
DISABLED,
#[doc = "Conversion on external event enabled"]
ENABLED,
}
impl EXTTRIGR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
EXTTRIGR::DISABLED => false,
EXTTRIGR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> EXTTRIGR {
match value {
false => EXTTRIGR::DISABLED,
true => EXTTRIGR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EXTTRIGR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == EXTTRIGR::ENABLED
}
}
#[doc = "Values that can be written to the field `EXTTRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTTRIGW {
#[doc = "Conversion on external event disabled"]
DISABLED,
#[doc = "Conversion on external event enabled"]
ENABLED,
}
impl EXTTRIGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
EXTTRIGW::DISABLED => false,
EXTTRIGW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _EXTTRIGW<'a> {
w: &'a mut W,
}
impl<'a> _EXTTRIGW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EXTTRIGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Conversion on external event disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(EXTTRIGW::DISABLED)
}
#[doc = "Conversion on external event enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(EXTTRIGW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 20);
self.w.bits |= ((value as u32) & 0x01) << 20;
self.w
}
}
#[doc = "Possible values of the field `EXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTSELR {
#[doc = "Timer 1 CC1 event"]
TIM1CC1,
#[doc = "Timer 1 CC2 event"]
TIM1CC2,
#[doc = "Timer 1 CC3 event"]
TIM1CC3,
#[doc = "Timer 2 CC2 event"]
TIM2CC2,
#[doc = "Timer 3 TRGO event"]
TIM3TRGO,
#[doc = "Timer 4 CC4 event"]
TIM4CC4,
#[doc = "EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)"]
EXTI11,
#[doc = "SWSTART"]
SWSTART,
}
impl EXTSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
EXTSELR::TIM1CC1 => 0,
EXTSELR::TIM1CC2 => 0x01,
EXTSELR::TIM1CC3 => 0x02,
EXTSELR::TIM2CC2 => 0x03,
EXTSELR::TIM3TRGO => 0x04,
EXTSELR::TIM4CC4 => 0x05,
EXTSELR::EXTI11 => 0x06,
EXTSELR::SWSTART => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> EXTSELR {
match value {
0 => EXTSELR::TIM1CC1,
1 => EXTSELR::TIM1CC2,
2 => EXTSELR::TIM1CC3,
3 => EXTSELR::TIM2CC2,
4 => EXTSELR::TIM3TRGO,
5 => EXTSELR::TIM4CC4,
6 => EXTSELR::EXTI11,
7 => EXTSELR::SWSTART,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TIM1CC1`"]
#[inline(always)]
pub fn is_tim1cc1(&self) -> bool {
*self == EXTSELR::TIM1CC1
}
#[doc = "Checks if the value of the field is `TIM1CC2`"]
#[inline(always)]
pub fn is_tim1cc2(&self) -> bool {
*self == EXTSELR::TIM1CC2
}
#[doc = "Checks if the value of the field is `TIM1CC3`"]
#[inline(always)]
pub fn is_tim1cc3(&self) -> bool {
*self == EXTSELR::TIM1CC3
}
#[doc = "Checks if the value of the field is `TIM2CC2`"]
#[inline(always)]
pub fn is_tim2cc2(&self) -> bool {
*self == EXTSELR::TIM2CC2
}
#[doc = "Checks if the value of the field is `TIM3TRGO`"]
#[inline(always)]
pub fn is_tim3trgo(&self) -> bool {
*self == EXTSELR::TIM3TRGO
}
#[doc = "Checks if the value of the field is `TIM4CC4`"]
#[inline(always)]
pub fn is_tim4cc4(&self) -> bool {
*self == EXTSELR::TIM4CC4
}
#[doc = "Checks if the value of the field is `EXTI11`"]
#[inline(always)]
pub fn is_exti11(&self) -> bool {
*self == EXTSELR::EXTI11
}
#[doc = "Checks if the value of the field is `SWSTART`"]
#[inline(always)]
pub fn is_swstart(&self) -> bool {
*self == EXTSELR::SWSTART
}
}
#[doc = "Values that can be written to the field `EXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTSELW {
#[doc = "Timer 1 CC1 event"]
TIM1CC1,
#[doc = "Timer 1 CC2 event"]
TIM1CC2,
#[doc = "Timer 1 CC3 event"]
TIM1CC3,
#[doc = "Timer 2 CC2 event"]
TIM2CC2,
#[doc = "Timer 3 TRGO event"]
TIM3TRGO,
#[doc = "Timer 4 CC4 event"]
TIM4CC4,
#[doc = "EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)"]
EXTI11,
#[doc = "SWSTART"]
SWSTART,
}
impl EXTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
EXTSELW::TIM1CC1 => 0,
EXTSELW::TIM1CC2 => 1,
EXTSELW::TIM1CC3 => 2,
EXTSELW::TIM2CC2 => 3,
EXTSELW::TIM3TRGO => 4,
EXTSELW::TIM4CC4 => 5,
EXTSELW::EXTI11 => 6,
EXTSELW::SWSTART => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _EXTSELW<'a> {
w: &'a mut W,
}
impl<'a> _EXTSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: EXTSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Timer 1 CC1 event"]
#[inline(always)]
pub fn tim1cc1(self) -> &'a mut W {
self.variant(EXTSELW::TIM1CC1)
}
#[doc = "Timer 1 CC2 event"]
#[inline(always)]
pub fn tim1cc2(self) -> &'a mut W {
self.variant(EXTSELW::TIM1CC2)
}
#[doc = "Timer 1 CC3 event"]
#[inline(always)]
pub fn tim1cc3(self) -> &'a mut W {
self.variant(EXTSELW::TIM1CC3)
}
#[doc = "Timer 2 CC2 event"]
#[inline(always)]
pub fn tim2cc2(self) -> &'a mut W {
self.variant(EXTSELW::TIM2CC2)
}
#[doc = "Timer 3 TRGO event"]
#[inline(always)]
pub fn tim3trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM3TRGO)
}
#[doc = "Timer 4 CC4 event"]
#[inline(always)]
pub fn tim4cc4(self) -> &'a mut W {
self.variant(EXTSELW::TIM4CC4)
}
#[doc = "EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)"]
#[inline(always)]
pub fn exti11(self) -> &'a mut W {
self.variant(EXTSELW::EXTI11)
}
#[doc = "SWSTART"]
#[inline(always)]
pub fn swstart(self) -> &'a mut W {
self.variant(EXTSELW::SWSTART)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 17);
self.w.bits |= ((value as u32) & 0x07) << 17;
self.w
}
}
#[doc = "Possible values of the field `JEXTTRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JEXTTRIGR {
#[doc = "Conversion on external event disabled"]
DISABLED,
#[doc = "Conversion on external event enabled"]
ENABLED,
}
impl JEXTTRIGR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
JEXTTRIGR::DISABLED => false,
JEXTTRIGR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> JEXTTRIGR {
match value {
false => JEXTTRIGR::DISABLED,
true => JEXTTRIGR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == JEXTTRIGR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == JEXTTRIGR::ENABLED
}
}
#[doc = "Values that can be written to the field `JEXTTRIG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JEXTTRIGW {
#[doc = "Conversion on external event disabled"]
DISABLED,
#[doc = "Conversion on external event enabled"]
ENABLED,
}
impl JEXTTRIGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
JEXTTRIGW::DISABLED => false,
JEXTTRIGW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _JEXTTRIGW<'a> {
w: &'a mut W,
}
impl<'a> _JEXTTRIGW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: JEXTTRIGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Conversion on external event disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(JEXTTRIGW::DISABLED)
}
#[doc = "Conversion on external event enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(JEXTTRIGW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = "Possible values of the field `JEXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JEXTSELR {
#[doc = "Timer 1 TRGO event"]
TIM1TRGO,
#[doc = "Timer 1 CC4 event"]
TIM1CC4,
#[doc = "Timer 2 TRGO event"]
TIM2TRGO,
#[doc = "Timer 2 CC1 event"]
TIM2CC1,
#[doc = "Timer 3 CC4 event"]
TIM3CC4,
#[doc = "Timer 4 TRGO event"]
TIM4TRGO,
#[doc = "EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)"]
EXTI15,
#[doc = "JSWSTART"]
JSWSTART,
}
impl JEXTSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
JEXTSELR::TIM1TRGO => 0,
JEXTSELR::TIM1CC4 => 0x01,
JEXTSELR::TIM2TRGO => 0x02,
JEXTSELR::TIM2CC1 => 0x03,
JEXTSELR::TIM3CC4 => 0x04,
JEXTSELR::TIM4TRGO => 0x05,
JEXTSELR::EXTI15 => 0x06,
JEXTSELR::JSWSTART => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> JEXTSELR {
match value {
0 => JEXTSELR::TIM1TRGO,
1 => JEXTSELR::TIM1CC4,
2 => JEXTSELR::TIM2TRGO,
3 => JEXTSELR::TIM2CC1,
4 => JEXTSELR::TIM3CC4,
5 => JEXTSELR::TIM4TRGO,
6 => JEXTSELR::EXTI15,
7 => JEXTSELR::JSWSTART,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TIM1TRGO`"]
#[inline(always)]
pub fn is_tim1trgo(&self) -> bool {
*self == JEXTSELR::TIM1TRGO
}
#[doc = "Checks if the value of the field is `TIM1CC4`"]
#[inline(always)]
pub fn is_tim1cc4(&self) -> bool {
*self == JEXTSELR::TIM1CC4
}
#[doc = "Checks if the value of the field is `TIM2TRGO`"]
#[inline(always)]
pub fn is_tim2trgo(&self) -> bool {
*self == JEXTSELR::TIM2TRGO
}
#[doc = "Checks if the value of the field is `TIM2CC1`"]
#[inline(always)]
pub fn is_tim2cc1(&self) -> bool {
*self == JEXTSELR::TIM2CC1
}
#[doc = "Checks if the value of the field is `TIM3CC4`"]
#[inline(always)]
pub fn is_tim3cc4(&self) -> bool {
*self == JEXTSELR::TIM3CC4
}
#[doc = "Checks if the value of the field is `TIM4TRGO`"]
#[inline(always)]
pub fn is_tim4trgo(&self) -> bool {
*self == JEXTSELR::TIM4TRGO
}
#[doc = "Checks if the value of the field is `EXTI15`"]
#[inline(always)]
pub fn is_exti15(&self) -> bool {
*self == JEXTSELR::EXTI15
}
#[doc = "Checks if the value of the field is `JSWSTART`"]
#[inline(always)]
pub fn is_jswstart(&self) -> bool {
*self == JEXTSELR::JSWSTART
}
}
#[doc = "Values that can be written to the field `JEXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JEXTSELW {
#[doc = "Timer 1 TRGO event"]
TIM1TRGO,
#[doc = "Timer 1 CC4 event"]
TIM1CC4,
#[doc = "Timer 2 TRGO event"]
TIM2TRGO,
#[doc = "Timer 2 CC1 event"]
TIM2CC1,
#[doc = "Timer 3 CC4 event"]
TIM3CC4,
#[doc = "Timer 4 TRGO event"]
TIM4TRGO,
#[doc = "EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)"]
EXTI15,
#[doc = "JSWSTART"]
JSWSTART,
}
impl JEXTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
JEXTSELW::TIM1TRGO => 0,
JEXTSELW::TIM1CC4 => 1,
JEXTSELW::TIM2TRGO => 2,
JEXTSELW::TIM2CC1 => 3,
JEXTSELW::TIM3CC4 => 4,
JEXTSELW::TIM4TRGO => 5,
JEXTSELW::EXTI15 => 6,
JEXTSELW::JSWSTART => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _JEXTSELW<'a> {
w: &'a mut W,
}
impl<'a> _JEXTSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: JEXTSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Timer 1 TRGO event"]
#[inline(always)]
pub fn tim1trgo(self) -> &'a mut W {
self.variant(JEXTSELW::TIM1TRGO)
}
#[doc = "Timer 1 CC4 event"]
#[inline(always)]
pub fn tim1cc4(self) -> &'a mut W {
self.variant(JEXTSELW::TIM1CC4)
}
#[doc = "Timer 2 TRGO event"]
#[inline(always)]
pub fn tim2trgo(self) -> &'a mut W {
self.variant(JEXTSELW::TIM2TRGO)
}
#[doc = "Timer 2 CC1 event"]
#[inline(always)]
pub fn tim2cc1(self) -> &'a mut W {
self.variant(JEXTSELW::TIM2CC1)
}
#[doc = "Timer 3 CC4 event"]
#[inline(always)]
pub fn tim3cc4(self) -> &'a mut W {
self.variant(JEXTSELW::TIM3CC4)
}
#[doc = "Timer 4 TRGO event"]
#[inline(always)]
pub fn tim4trgo(self) -> &'a mut W {
self.variant(JEXTSELW::TIM4TRGO)
}
#[doc = "EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)"]
#[inline(always)]
pub fn exti15(self) -> &'a mut W {
self.variant(JEXTSELW::EXTI15)
}
#[doc = "JSWSTART"]
#[inline(always)]
pub fn jswstart(self) -> &'a mut W {
self.variant(JEXTSELW::JSWSTART)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 12);
self.w.bits |= ((value as u32) & 0x07) << 12;
self.w
}
}
#[doc = "Possible values of the field `ALIGN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALIGNR {
#[doc = "Right Alignment"]
RIGHT,
#[doc = "Left Alignment"]
LEFT,
}
impl ALIGNR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
ALIGNR::RIGHT => false,
ALIGNR::LEFT => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> ALIGNR {
match value {
false => ALIGNR::RIGHT,
true => ALIGNR::LEFT,
}
}
#[doc = "Checks if the value of the field is `RIGHT`"]
#[inline(always)]
pub fn is_right(&self) -> bool {
*self == ALIGNR::RIGHT
}
#[doc = "Checks if the value of the field is `LEFT`"]
#[inline(always)]
pub fn is_left(&self) -> bool {
*self == ALIGNR::LEFT
}
}
#[doc = "Values that can be written to the field `ALIGN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALIGNW {
#[doc = "Right Alignment"]
RIGHT,
#[doc = "Left Alignment"]
LEFT,
}
impl ALIGNW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
ALIGNW::RIGHT => false,
ALIGNW::LEFT => true,
}
}
}
#[doc = r"Proxy"]
pub struct _ALIGNW<'a> {
w: &'a mut W,
}
impl<'a> _ALIGNW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ALIGNW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Right Alignment"]
#[inline(always)]
pub fn right(self) -> &'a mut W {
self.variant(ALIGNW::RIGHT)
}
#[doc = "Left Alignment"]
#[inline(always)]
pub fn left(self) -> &'a mut W {
self.variant(ALIGNW::LEFT)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 11);
self.w.bits |= ((value as u32) & 0x01) << 11;
self.w
}
}
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "DMA mode disabled"]
DISABLED,
#[doc = "DMA mode enabled"]
ENABLED,
}
impl DMAR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
DMAR::DISABLED => false,
DMAR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> DMAR {
match value {
false => DMAR::DISABLED,
true => DMAR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == DMAR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == DMAR::ENABLED
}
}
#[doc = "Values that can be written to the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAW {
#[doc = "DMA mode disabled"]
DISABLED,
#[doc = "DMA mode enabled"]
ENABLED,
}
impl DMAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
DMAW::DISABLED => false,
DMAW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _DMAW<'a> {
w: &'a mut W,
}
impl<'a> _DMAW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA mode disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DMAW::DISABLED)
}
#[doc = "DMA mode enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DMAW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `RSTCAL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RSTCALR {
#[doc = "Calibration register initialized"]
INITIALIZED,
#[doc = "Initializing calibration register"]
NOTINITIALIZED,
}
impl RSTCALR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
RSTCALR::INITIALIZED => false,
RSTCALR::NOTINITIALIZED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> RSTCALR {
match value {
false => RSTCALR::INITIALIZED,
true => RSTCALR::NOTINITIALIZED,
}
}
#[doc = "Checks if the value of the field is `INITIALIZED`"]
#[inline(always)]
pub fn is_initialized(&self) -> bool {
*self == RSTCALR::INITIALIZED
}
#[doc = "Checks if the value of the field is `NOTINITIALIZED`"]
#[inline(always)]
pub fn is_not_initialized(&self) -> bool {
*self == RSTCALR::NOTINITIALIZED
}
}
#[doc = "Values that can be written to the field `RSTCAL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RSTCALW {
#[doc = "Initialize calibration register"]
INITIALIZE,
}
impl RSTCALW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
RSTCALW::INITIALIZE => true,
}
}
}
#[doc = r"Proxy"]
pub struct _RSTCALW<'a> {
w: &'a mut W,
}
impl<'a> _RSTCALW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RSTCALW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Initialize calibration register"]
#[inline(always)]
pub fn initialize(self) -> &'a mut W {
self.variant(RSTCALW::INITIALIZE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 3);
self.w.bits |= ((value as u32) & 0x01) << 3;
self.w
}
}
#[doc = "Possible values of the field `CAL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CALR {
#[doc = "Calibration completed"]
COMPLETE,
#[doc = "Calibrating"]
NOTCOMPLETE,
}
impl CALR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CALR::COMPLETE => false,
CALR::NOTCOMPLETE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CALR {
match value {
false => CALR::COMPLETE,
true => CALR::NOTCOMPLETE,
}
}
#[doc = "Checks if the value of the field is `COMPLETE`"]
#[inline(always)]
pub fn is_complete(&self) -> bool {
*self == CALR::COMPLETE
}
#[doc = "Checks if the value of the field is `NOTCOMPLETE`"]
#[inline(always)]
pub fn is_not_complete(&self) -> bool {
*self == CALR::NOTCOMPLETE
}
}
#[doc = "Values that can be written to the field `CAL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CALW {
#[doc = "Enable calibration"]
START,
}
impl CALW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CALW::START => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CALW<'a> {
w: &'a mut W,
}
impl<'a> _CALW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CALW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Enable calibration"]
#[inline(always)]
pub fn start(self) -> &'a mut W {
self.variant(CALW::START)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 2);
self.w.bits |= ((value as u32) & 0x01) << 2;
self.w
}
}
#[doc = "Possible values of the field `CONT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CONTR {
#[doc = "Single conversion mode"]
SINGLE,
#[doc = "Continuous conversion mode"]
CONTINUOUS,
}
impl CONTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CONTR::SINGLE => false,
CONTR::CONTINUOUS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CONTR {
match value {
false => CONTR::SINGLE,
true => CONTR::CONTINUOUS,
}
}
#[doc = "Checks if the value of the field is `SINGLE`"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == CONTR::SINGLE
}
#[doc = "Checks if the value of the field is `CONTINUOUS`"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == CONTR::CONTINUOUS
}
}
#[doc = "Values that can be written to the field `CONT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CONTW {
#[doc = "Single conversion mode"]
SINGLE,
#[doc = "Continuous conversion mode"]
CONTINUOUS,
}
impl CONTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CONTW::SINGLE => false,
CONTW::CONTINUOUS => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CONTW<'a> {
w: &'a mut W,
}
impl<'a> _CONTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CONTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single conversion mode"]
#[inline(always)]
pub fn single(self) -> &'a mut W {
self.variant(CONTW::SINGLE)
}
#[doc = "Continuous conversion mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut W {
self.variant(CONTW::CONTINUOUS)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 1);
self.w.bits |= ((value as u32) & 0x01) << 1;
self.w
}
}
#[doc = "Possible values of the field `ADON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADONR {
#[doc = "Disable ADC conversion/calibration and go to power down mode"]
DISABLED,
#[doc = "Enable ADC and to start conversion"]
ENABLED,
}
impl ADONR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
ADONR::DISABLED => false,
ADONR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> ADONR {
match value {
false => ADONR::DISABLED,
true => ADONR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADONR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADONR::ENABLED
}
}
#[doc = "Values that can be written to the field `ADON`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADONW {
#[doc = "Disable ADC conversion/calibration and go to power down mode"]
DISABLED,
#[doc = "Enable ADC and to start conversion"]
ENABLED,
}
impl ADONW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
ADONW::DISABLED => false,
ADONW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _ADONW<'a> {
w: &'a mut W,
}
impl<'a> _ADONW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADONW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Disable ADC conversion/calibration and go to power down mode"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(ADONW::DISABLED)
}
#[doc = "Enable ADC and to start conversion"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(ADONW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 0);
self.w.bits |= ((value as u32) & 0x01) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 23 - Temperature sensor and VREFINT enable"]
#[inline(always)]
pub fn tsvrefe(&self) -> TSVREFER {
TSVREFER::_from(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 22 - Start conversion of regular channels"]
#[inline(always)]
pub fn swstart(&self) -> SWSTARTR {
SWSTARTR::_from(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 21 - Start conversion of injected channels"]
#[inline(always)]
pub fn jswstart(&self) -> JSWSTARTR {
JSWSTARTR::_from(((self.bits >> 21) & 0x01) != 0)
}
#[doc = "Bit 20 - External trigger conversion mode for regular channels"]
#[inline(always)]
pub fn exttrig(&self) -> EXTTRIGR {
EXTTRIGR::_from(((self.bits >> 20) & 0x01) != 0)
}
#[doc = "Bits 17:19 - External event select for regular group"]
#[inline(always)]
pub fn extsel(&self) -> EXTSELR {
EXTSELR::_from(((self.bits >> 17) & 0x07) as u8)
}
#[doc = "Bit 15 - External trigger conversion mode for injected channels"]
#[inline(always)]
pub fn jexttrig(&self) -> JEXTTRIGR {
JEXTTRIGR::_from(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bits 12:14 - External event select for injected group"]
#[inline(always)]
pub fn jextsel(&self) -> JEXTSELR {
JEXTSELR::_from(((self.bits >> 12) & 0x07) as u8)
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
pub fn align(&self) -> ALIGNR {
ALIGNR::_from(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 8 - Direct memory access mode"]
#[inline(always)]
pub fn dma(&self) -> DMAR {
DMAR::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 3 - Reset calibration"]
#[inline(always)]
pub fn rstcal(&self) -> RSTCALR {
RSTCALR::_from(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - A/D calibration"]
#[inline(always)]
pub fn cal(&self) -> CALR {
CALR::_from(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
pub fn cont(&self) -> CONTR {
CONTR::_from(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 0 - A/D converter ON / OFF"]
#[inline(always)]
pub fn adon(&self) -> ADONR {
ADONR::_from(((self.bits >> 0) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 23 - Temperature sensor and VREFINT enable"]
#[inline(always)]
pub fn tsvrefe(&mut self) -> _TSVREFEW {
_TSVREFEW { w: self }
}
#[doc = "Bit 22 - Start conversion of regular channels"]
#[inline(always)]
pub fn swstart(&mut self) -> _SWSTARTW {
_SWSTARTW { w: self }
}
#[doc = "Bit 21 - Start conversion of injected channels"]
#[inline(always)]
pub fn jswstart(&mut self) -> _JSWSTARTW {
_JSWSTARTW { w: self }
}
#[doc = "Bit 20 - External trigger conversion mode for regular channels"]
#[inline(always)]
pub fn exttrig(&mut self) -> _EXTTRIGW {
_EXTTRIGW { w: self }
}
#[doc = "Bits 17:19 - External event select for regular group"]
#[inline(always)]
pub fn extsel(&mut self) -> _EXTSELW {
_EXTSELW { w: self }
}
#[doc = "Bit 15 - External trigger conversion mode for injected channels"]
#[inline(always)]
pub fn jexttrig(&mut self) -> _JEXTTRIGW {
_JEXTTRIGW { w: self }
}
#[doc = "Bits 12:14 - External event select for injected group"]
#[inline(always)]
pub fn jextsel(&mut self) -> _JEXTSELW {
_JEXTSELW { w: self }
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
pub fn align(&mut self) -> _ALIGNW {
_ALIGNW { w: self }
}
#[doc = "Bit 8 - Direct memory access mode"]
#[inline(always)]
pub fn dma(&mut self) -> _DMAW {
_DMAW { w: self }
}
#[doc = "Bit 3 - Reset calibration"]
#[inline(always)]
pub fn rstcal(&mut self) -> _RSTCALW {
_RSTCALW { w: self }
}
#[doc = "Bit 2 - A/D calibration"]
#[inline(always)]
pub fn cal(&mut self) -> _CALW {
_CALW { w: self }
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
pub fn cont(&mut self) -> _CONTW {
_CONTW { w: self }
}
#[doc = "Bit 0 - A/D converter ON / OFF"]
#[inline(always)]
pub fn adon(&mut self) -> _ADONW {
_ADONW { w: self }
}
}