#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SMPR1 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `SMP10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMP10R {
#[doc = "1.5 ADC clock cycles"]
CYCLES1_5,
#[doc = "7.5 ADC clock cycles"]
CYCLES7_5,
#[doc = "13.5 ADC clock cycles"]
CYCLES13_5,
#[doc = "28.5 ADC clock cycles"]
CYCLES28_5,
#[doc = "41.5 ADC clock cycles"]
CYCLES41_5,
#[doc = "55.5 ADC clock cycles"]
CYCLES55_5,
#[doc = "71.5 ADC clock cycles"]
CYCLES71_5,
#[doc = "239.5 ADC clock cycles"]
CYCLES239_5,
}
impl SMP10R {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SMP10R::CYCLES1_5 => 0,
SMP10R::CYCLES7_5 => 0x01,
SMP10R::CYCLES13_5 => 0x02,
SMP10R::CYCLES28_5 => 0x03,
SMP10R::CYCLES41_5 => 0x04,
SMP10R::CYCLES55_5 => 0x05,
SMP10R::CYCLES71_5 => 0x06,
SMP10R::CYCLES239_5 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SMP10R {
match value {
0 => SMP10R::CYCLES1_5,
1 => SMP10R::CYCLES7_5,
2 => SMP10R::CYCLES13_5,
3 => SMP10R::CYCLES28_5,
4 => SMP10R::CYCLES41_5,
5 => SMP10R::CYCLES55_5,
6 => SMP10R::CYCLES71_5,
7 => SMP10R::CYCLES239_5,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `CYCLES1_5`"]
#[inline(always)]
pub fn is_cycles1_5(&self) -> bool {
*self == SMP10R::CYCLES1_5
}
#[doc = "Checks if the value of the field is `CYCLES7_5`"]
#[inline(always)]
pub fn is_cycles7_5(&self) -> bool {
*self == SMP10R::CYCLES7_5
}
#[doc = "Checks if the value of the field is `CYCLES13_5`"]
#[inline(always)]
pub fn is_cycles13_5(&self) -> bool {
*self == SMP10R::CYCLES13_5
}
#[doc = "Checks if the value of the field is `CYCLES28_5`"]
#[inline(always)]
pub fn is_cycles28_5(&self) -> bool {
*self == SMP10R::CYCLES28_5
}
#[doc = "Checks if the value of the field is `CYCLES41_5`"]
#[inline(always)]
pub fn is_cycles41_5(&self) -> bool {
*self == SMP10R::CYCLES41_5
}
#[doc = "Checks if the value of the field is `CYCLES55_5`"]
#[inline(always)]
pub fn is_cycles55_5(&self) -> bool {
*self == SMP10R::CYCLES55_5
}
#[doc = "Checks if the value of the field is `CYCLES71_5`"]
#[inline(always)]
pub fn is_cycles71_5(&self) -> bool {
*self == SMP10R::CYCLES71_5
}
#[doc = "Checks if the value of the field is `CYCLES239_5`"]
#[inline(always)]
pub fn is_cycles239_5(&self) -> bool {
*self == SMP10R::CYCLES239_5
}
}
#[doc = "Values that can be written to the field `SMP10`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SMP10W {
#[doc = "1.5 ADC clock cycles"]
CYCLES1_5,
#[doc = "7.5 ADC clock cycles"]
CYCLES7_5,
#[doc = "13.5 ADC clock cycles"]
CYCLES13_5,
#[doc = "28.5 ADC clock cycles"]
CYCLES28_5,
#[doc = "41.5 ADC clock cycles"]
CYCLES41_5,
#[doc = "55.5 ADC clock cycles"]
CYCLES55_5,
#[doc = "71.5 ADC clock cycles"]
CYCLES71_5,
#[doc = "239.5 ADC clock cycles"]
CYCLES239_5,
}
impl SMP10W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SMP10W::CYCLES1_5 => 0,
SMP10W::CYCLES7_5 => 1,
SMP10W::CYCLES13_5 => 2,
SMP10W::CYCLES28_5 => 3,
SMP10W::CYCLES41_5 => 4,
SMP10W::CYCLES55_5 => 5,
SMP10W::CYCLES71_5 => 6,
SMP10W::CYCLES239_5 => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _SMP10W<'a> {
w: &'a mut W,
}
impl<'a> _SMP10W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP10W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 0);
self.w.bits |= ((value as u32) & 0x07) << 0;
self.w
}
}
#[doc = "Possible values of the field `SMP11`"]
pub type SMP11R = SMP10R;
#[doc = "Values that can be written to the field `SMP11`"]
pub type SMP11W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP11W<'a> {
w: &'a mut W,
}
impl<'a> _SMP11W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP11W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 3);
self.w.bits |= ((value as u32) & 0x07) << 3;
self.w
}
}
#[doc = "Possible values of the field `SMP12`"]
pub type SMP12R = SMP10R;
#[doc = "Values that can be written to the field `SMP12`"]
pub type SMP12W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP12W<'a> {
w: &'a mut W,
}
impl<'a> _SMP12W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP12W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 6);
self.w.bits |= ((value as u32) & 0x07) << 6;
self.w
}
}
#[doc = "Possible values of the field `SMP13`"]
pub type SMP13R = SMP10R;
#[doc = "Values that can be written to the field `SMP13`"]
pub type SMP13W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP13W<'a> {
w: &'a mut W,
}
impl<'a> _SMP13W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP13W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 9);
self.w.bits |= ((value as u32) & 0x07) << 9;
self.w
}
}
#[doc = "Possible values of the field `SMP14`"]
pub type SMP14R = SMP10R;
#[doc = "Values that can be written to the field `SMP14`"]
pub type SMP14W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP14W<'a> {
w: &'a mut W,
}
impl<'a> _SMP14W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP14W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 12);
self.w.bits |= ((value as u32) & 0x07) << 12;
self.w
}
}
#[doc = "Possible values of the field `SMP15`"]
pub type SMP15R = SMP10R;
#[doc = "Values that can be written to the field `SMP15`"]
pub type SMP15W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP15W<'a> {
w: &'a mut W,
}
impl<'a> _SMP15W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP15W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 15);
self.w.bits |= ((value as u32) & 0x07) << 15;
self.w
}
}
#[doc = "Possible values of the field `SMP16`"]
pub type SMP16R = SMP10R;
#[doc = "Values that can be written to the field `SMP16`"]
pub type SMP16W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP16W<'a> {
w: &'a mut W,
}
impl<'a> _SMP16W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP16W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 18);
self.w.bits |= ((value as u32) & 0x07) << 18;
self.w
}
}
#[doc = "Possible values of the field `SMP17`"]
pub type SMP17R = SMP10R;
#[doc = "Values that can be written to the field `SMP17`"]
pub type SMP17W = SMP10W;
#[doc = r"Proxy"]
pub struct _SMP17W<'a> {
w: &'a mut W,
}
impl<'a> _SMP17W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SMP17W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "1.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles1_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES1_5)
}
#[doc = "7.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles7_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES7_5)
}
#[doc = "13.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles13_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES13_5)
}
#[doc = "28.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles28_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES28_5)
}
#[doc = "41.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles41_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES41_5)
}
#[doc = "55.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles55_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES55_5)
}
#[doc = "71.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles71_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES71_5)
}
#[doc = "239.5 ADC clock cycles"]
#[inline(always)]
pub fn cycles239_5(self) -> &'a mut W {
self.variant(SMP10W::CYCLES239_5)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 21);
self.w.bits |= ((value as u32) & 0x07) << 21;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Channel 10 sample time selection"]
#[inline(always)]
pub fn smp10(&self) -> SMP10R {
SMP10R::_from(((self.bits >> 0) & 0x07) as u8)
}
#[doc = "Bits 3:5 - Channel 11 sample time selection"]
#[inline(always)]
pub fn smp11(&self) -> SMP11R {
SMP11R::_from(((self.bits >> 3) & 0x07) as u8)
}
#[doc = "Bits 6:8 - Channel 12 sample time selection"]
#[inline(always)]
pub fn smp12(&self) -> SMP12R {
SMP12R::_from(((self.bits >> 6) & 0x07) as u8)
}
#[doc = "Bits 9:11 - Channel 13 sample time selection"]
#[inline(always)]
pub fn smp13(&self) -> SMP13R {
SMP13R::_from(((self.bits >> 9) & 0x07) as u8)
}
#[doc = "Bits 12:14 - Channel 14 sample time selection"]
#[inline(always)]
pub fn smp14(&self) -> SMP14R {
SMP14R::_from(((self.bits >> 12) & 0x07) as u8)
}
#[doc = "Bits 15:17 - Channel 15 sample time selection"]
#[inline(always)]
pub fn smp15(&self) -> SMP15R {
SMP15R::_from(((self.bits >> 15) & 0x07) as u8)
}
#[doc = "Bits 18:20 - Channel 16 sample time selection"]
#[inline(always)]
pub fn smp16(&self) -> SMP16R {
SMP16R::_from(((self.bits >> 18) & 0x07) as u8)
}
#[doc = "Bits 21:23 - Channel 17 sample time selection"]
#[inline(always)]
pub fn smp17(&self) -> SMP17R {
SMP17R::_from(((self.bits >> 21) & 0x07) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Channel 10 sample time selection"]
#[inline(always)]
pub fn smp10(&mut self) -> _SMP10W {
_SMP10W { w: self }
}
#[doc = "Bits 3:5 - Channel 11 sample time selection"]
#[inline(always)]
pub fn smp11(&mut self) -> _SMP11W {
_SMP11W { w: self }
}
#[doc = "Bits 6:8 - Channel 12 sample time selection"]
#[inline(always)]
pub fn smp12(&mut self) -> _SMP12W {
_SMP12W { w: self }
}
#[doc = "Bits 9:11 - Channel 13 sample time selection"]
#[inline(always)]
pub fn smp13(&mut self) -> _SMP13W {
_SMP13W { w: self }
}
#[doc = "Bits 12:14 - Channel 14 sample time selection"]
#[inline(always)]
pub fn smp14(&mut self) -> _SMP14W {
_SMP14W { w: self }
}
#[doc = "Bits 15:17 - Channel 15 sample time selection"]
#[inline(always)]
pub fn smp15(&mut self) -> _SMP15W {
_SMP15W { w: self }
}
#[doc = "Bits 18:20 - Channel 16 sample time selection"]
#[inline(always)]
pub fn smp16(&mut self) -> _SMP16W {
_SMP16W { w: self }
}
#[doc = "Bits 21:23 - Channel 17 sample time selection"]
#[inline(always)]
pub fn smp17(&mut self) -> _SMP17W {
_SMP17W { w: self }
}
}