#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Timer {
ptr: *mut u8,
}
unsafe impl Send for Timer {}
unsafe impl Sync for Timer {}
impl Timer {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Write to bits 63:32 of time always write timelw before timehw"]
#[inline(always)]
pub const fn timehw(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"]
#[inline(always)]
pub const fn timelw(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Read from bits 63:32 of time always read timelr before timehr"]
#[inline(always)]
pub const fn timehr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "Read from bits 31:0 of time"]
#[inline(always)]
pub const fn timelr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."]
#[inline(always)]
pub const fn alarm(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize + n * 4usize) as _) }
}
#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."]
#[inline(always)]
pub const fn armed(self) -> crate::common::Reg<regs::Armed, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "Raw read from bits 63:32 of time (no side effects)"]
#[inline(always)]
pub const fn timerawh(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "Raw read from bits 31:0 of time (no side effects)"]
#[inline(always)]
pub const fn timerawl(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "Set bits high to enable pause when the corresponding debug ports are active"]
#[inline(always)]
pub const fn dbgpause(self) -> crate::common::Reg<regs::Dbgpause, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "Set high to pause the timer"]
#[inline(always)]
pub const fn pause(self) -> crate::common::Reg<regs::Pause, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"]
#[inline(always)]
pub const fn locked(self) -> crate::common::Reg<regs::Locked, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
#[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."]
#[inline(always)]
pub const fn source(self) -> crate::common::Reg<regs::Source, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "Raw Interrupts"]
#[inline(always)]
pub const fn intr(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "Interrupt Enable"]
#[inline(always)]
pub const fn inte(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "Interrupt Force"]
#[inline(always)]
pub const fn intf(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "Interrupt status after masking & forcing"]
#[inline(always)]
pub const fn ints(self) -> crate::common::Reg<regs::Int, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
}
pub mod regs;
pub mod vals;