#[doc = "Hardware access control registers"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Accessctrl {
ptr: *mut u8,
}
unsafe impl Send for Accessctrl {}
unsafe impl Sync for Accessctrl {}
impl Accessctrl {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."]
#[inline(always)]
pub const fn lock(self) -> crate::common::Reg<regs::Lock, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."]
#[inline(always)]
pub const fn force_core_ns(self) -> crate::common::Reg<regs::ForceCoreNs, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."]
#[inline(always)]
pub const fn cfgreset(self) -> crate::common::Reg<regs::Cfgreset, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access"]
#[inline(always)]
pub const fn gpio_nsmask0(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."]
#[inline(always)]
pub const fn gpio_nsmask1(self) -> crate::common::Reg<regs::GpioNsmask1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn rom(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn xip_main(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn sram(self, n: usize) -> crate::common::Reg<regs::Access, crate::common::RW> {
assert!(n < 10usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize + n * 4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn dma(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn usbctrl(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pio0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pio1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pio2(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn coresight_trace(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn coresight_periph(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn sysinfo(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn resets(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn io_bank0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn io_bank1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pads_bank0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pads_qspi(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn busctrl(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn adc0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn hstx(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn i2c0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn i2c1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pwm(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn spi0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn spi1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn timer0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x98usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn timer1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn uart0(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn uart1(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn otp(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn tbman(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xacusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn powman(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn trng(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn sha256(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn syscfg(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn clocks(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn xosc(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn rosc(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pll_sys(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn pll_usb(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn ticks(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn watchdog(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn rsm(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn xip_ctrl(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn xip_qmi(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) }
}
#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."]
#[inline(always)]
pub const fn xip_aux(self) -> crate::common::Reg<regs::Access, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) }
}
}
pub mod regs;