Docs.rs
riscv-0.16.0
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riscv32i-unknown-none-elf
riscv32imac-unknown-none-elf
riscv32imc-unknown-none-elf
riscv64gc-unknown-none-elf
riscv64imac-unknown-none-elf
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riscv 0.16.0
Low level access to RISC-V processors
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tests
cycle.rs
cycleh.rs
dcsr.rs
dpc.rs
dscratch0.rs
dscratch1.rs
hpmcounterx.rs
instret.rs
instreth.rs
macros.rs
marchid.rs
mcause.rs
mconfigptr.rs
mcounteren.rs
mcountinhibit.rs
mcycle.rs
mcycleh.rs
medeleg.rs
mepc.rs
mhartid.rs
mhpmcounterx.rs
mhpmeventx.rs
mideleg.rs
mie.rs
mimpid.rs
minstret.rs
minstreth.rs
mip.rs
misa.rs
miselect.rs
mscratch.rs
mseccfg.rs
mseccfgh.rs
mstatus.rs
mstatush.rs
mtinst.rs
mtopi.rs
mtval.rs
mtval2.rs
mtvec.rs
mvendorid.rs
mvien.rs
mvienh.rs
pmpaddrx.rs
pmpcfgx.rs
satp.rs
scause.rs
scontext.rs
scounteren.rs
senvcfg.rs
sepc.rs
sie.rs
sip.rs
sscratch.rs
sstatus.rs
stval.rs
stvec.rs
tests.rs
time.rs
timeh.rs
vstopi.rs
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//!
minstreth register
read_csr_as_usize_rv32!
(
0xB82
)
;
write_csr_as_usize_rv32!
(
0xB82
)
;