rigless 0.0.2

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; needs the rigless-sidecar package from rigless-labs/qemu
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `UART4` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `SR` at offset `0x0`, resets to `0x00C0_0000`, read-write.
    Sr = 0,
    /// `DR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Dr = 1,
    /// `BRR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Brr = 2,
    /// `CR1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cr1 = 3,
    /// `CR2` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Cr2 = 4,
    /// `CR3` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Cr3 = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Sr, Self::Dr, Self::Brr, Self::Cr1, Self::Cr2, Self::Cr3];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `PE`, bit 0, read-only.
    pub const PE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `FE`, bit 1, read-only.
    pub const FE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `NF`, bit 2, read-only.
    pub const NF: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `ORE`, bit 3, read-only.
    pub const ORE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `IDLE`, bit 4, read-only.
    pub const IDLE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `RXNE`, bit 5.
    pub const RXNE: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `TC`, bit 6.
    pub const TC: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TXE`, bit 7, read-only.
    pub const TXE: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `LBD`, bit 8.
    pub const LBD: &FieldSpec = &super::REGISTERS[0].fields[8];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DR`, bits 0..=8.
    pub const DR: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `BRR`.
pub mod brr {
    use super::FieldSpec;
    /// `DIV_Fraction`, bits 0..=3.
    pub const DIV_FRACTION: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `DIV_Mantissa`, bits 4..=15.
    pub const DIV_MANTISSA: &FieldSpec = &super::REGISTERS[2].fields[1];
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `SBK`, bit 0.
    pub const SBK: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `RWU`, bit 1.
    pub const RWU: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `RE`, bit 2.
    pub const RE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `TE`, bit 3.
    pub const TE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `IDLEIE`, bit 4.
    pub const IDLEIE: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `RXNEIE`, bit 5.
    pub const RXNEIE: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `TCIE`, bit 6.
    pub const TCIE: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `TXEIE`, bit 7.
    pub const TXEIE: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `PEIE`, bit 8.
    pub const PEIE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `PS`, bit 9.
    pub const PS: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `PCE`, bit 10.
    pub const PCE: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `WAKE`, bit 11.
    pub const WAKE: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `M`, bit 12.
    pub const M: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `UE`, bit 13.
    pub const UE: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `OVER8`, bit 15.
    pub const OVER8: &FieldSpec = &super::REGISTERS[3].fields[14];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `ADD`, bits 0..=3.
    pub const ADD: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `LBDL`, bit 5.
    pub const LBDL: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `LBDIE`, bit 6.
    pub const LBDIE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `STOP`, bits 12..=13.
    pub const STOP: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `LINEN`, bit 14.
    pub const LINEN: &FieldSpec = &super::REGISTERS[4].fields[4];
}

/// The fields of `CR3`.
pub mod cr3 {
    use super::FieldSpec;
    /// `EIE`, bit 0.
    pub const EIE: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `IREN`, bit 1.
    pub const IREN: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `IRLP`, bit 2.
    pub const IRLP: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `HDSEL`, bit 3.
    pub const HDSEL: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `DMAR`, bit 6.
    pub const DMAR: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `DMAT`, bit 7.
    pub const DMAT: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `ONEBIT`, bit 11.
    pub const ONEBIT: &FieldSpec = &super::REGISTERS[5].fields[6];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "SR", offset: 0x0, width: Width::W32, reset: 0x00C0_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ORE", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDLE", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXE", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBD", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DR", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BRR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DIV_Fraction", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIV_Mantissa", bit: 4, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SBK", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWU", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDLEIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNEIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAKE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "M", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVER8", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADD", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBDL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LBDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOP", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR3", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IREN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IRLP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HDSEL", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAR", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAT", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ONEBIT", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];