rigless 0.0.2

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `SDIO` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `POWER` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Power = 0,
    /// `CLKCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Clkcr = 1,
    /// `ARG` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Arg = 2,
    /// `CMD` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cmd = 3,
    /// `RESPCMD` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Respcmd = 4,
    /// `RESP1` at offset `0x14`, resets to `0x0000_0000`, read-only.
    Resp1 = 5,
    /// `RESP2` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Resp2 = 6,
    /// `RESP3` at offset `0x1C`, resets to `0x0000_0000`, read-only.
    Resp3 = 7,
    /// `RESP4` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Resp4 = 8,
    /// `DTIMER` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Dtimer = 9,
    /// `DLEN` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Dlen = 10,
    /// `DCTRL` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Dctrl = 11,
    /// `DCOUNT` at offset `0x30`, resets to `0x0000_0000`, read-only.
    Dcount = 12,
    /// `STA` at offset `0x34`, resets to `0x0000_0000`, read-only.
    Sta = 13,
    /// `ICR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Icr = 14,
    /// `MASK` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Mask = 15,
    /// `FIFOCNT` at offset `0x48`, resets to `0x0000_0000`, read-only.
    Fifocnt = 16,
    /// `FIFO` at offset `0x80`, resets to `0x0000_0000`, read-write.
    Fifo = 17,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 18] = [Self::Power, Self::Clkcr, Self::Arg, Self::Cmd, Self::Respcmd, Self::Resp1, Self::Resp2, Self::Resp3, Self::Resp4, Self::Dtimer, Self::Dlen, Self::Dctrl, Self::Dcount, Self::Sta, Self::Icr, Self::Mask, Self::Fifocnt, Self::Fifo];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `POWER`.
pub mod power {
    use super::FieldSpec;
    /// `PWRCTRL`, bits 0..=1.
    pub const PWRCTRL: &FieldSpec = &super::REGISTERS[0].fields[0];
}

/// The fields of `CLKCR`.
pub mod clkcr {
    use super::FieldSpec;
    /// `CLKDIV`, bits 0..=7.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CLKEN`, bit 8.
    pub const CLKEN: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `PWRSAV`, bit 9.
    pub const PWRSAV: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `BYPASS`, bit 10.
    pub const BYPASS: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `WIDBUS`, bits 11..=12.
    pub const WIDBUS: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `NEGEDGE`, bit 13.
    pub const NEGEDGE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `HWFC_EN`, bit 14.
    pub const HWFC_EN: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `ARG`.
pub mod arg {
    use super::FieldSpec;
    /// `CMDARG`, bits 0..=31.
    pub const CMDARG: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `CMD`.
pub mod cmd {
    use super::FieldSpec;
    /// `CMDINDEX`, bits 0..=5.
    pub const CMDINDEX: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `WAITRESP`, bits 6..=7.
    pub const WAITRESP: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `WAITINT`, bit 8.
    pub const WAITINT: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `WAITPEND`, bit 9.
    pub const WAITPEND: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CPSMEN`, bit 10.
    pub const CPSMEN: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `SDIOSuspend`, bit 11.
    pub const SDIOSUSPEND: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `ENCMDcompl`, bit 12.
    pub const ENCMDCOMPL: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `nIEN`, bit 13.
    pub const NIEN: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `CE_ATACMD`, bit 14.
    pub const CE_ATACMD: &FieldSpec = &super::REGISTERS[3].fields[8];
}

/// The fields of `RESPCMD`.
pub mod respcmd {
    use super::FieldSpec;
    /// `RESPCMD`, bits 0..=5.
    pub const RESPCMD: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `RESP1`.
pub mod resp1 {
    use super::FieldSpec;
    /// `CARDSTATUS1`, bits 0..=31.
    pub const CARDSTATUS1: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `RESP2`.
pub mod resp2 {
    use super::FieldSpec;
    /// `CARDSTATUS2`, bits 0..=31.
    pub const CARDSTATUS2: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `RESP3`.
pub mod resp3 {
    use super::FieldSpec;
    /// `CARDSTATUS3`, bits 0..=31.
    pub const CARDSTATUS3: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `RESP4`.
pub mod resp4 {
    use super::FieldSpec;
    /// `CARDSTATUS4`, bits 0..=31.
    pub const CARDSTATUS4: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `DTIMER`.
pub mod dtimer {
    use super::FieldSpec;
    /// `DATATIME`, bits 0..=31.
    pub const DATATIME: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `DLEN`.
pub mod dlen {
    use super::FieldSpec;
    /// `DATALENGTH`, bits 0..=24.
    pub const DATALENGTH: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `DCTRL`.
pub mod dctrl {
    use super::FieldSpec;
    /// `DTEN`, bit 0.
    pub const DTEN: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `DTDIR`, bit 1.
    pub const DTDIR: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `DTMODE`, bit 2.
    pub const DTMODE: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `DMAEN`, bit 3.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `DBLOCKSIZE`, bits 4..=7.
    pub const DBLOCKSIZE: &FieldSpec = &super::REGISTERS[11].fields[4];
    /// `RWSTART`, bit 8.
    pub const RWSTART: &FieldSpec = &super::REGISTERS[11].fields[5];
    /// `RWSTOP`, bit 9.
    pub const RWSTOP: &FieldSpec = &super::REGISTERS[11].fields[6];
    /// `RWMOD`, bit 10.
    pub const RWMOD: &FieldSpec = &super::REGISTERS[11].fields[7];
    /// `SDIOEN`, bit 11.
    pub const SDIOEN: &FieldSpec = &super::REGISTERS[11].fields[8];
}

/// The fields of `DCOUNT`.
pub mod dcount {
    use super::FieldSpec;
    /// `DATACOUNT`, bits 0..=24.
    pub const DATACOUNT: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `STA`.
pub mod sta {
    use super::FieldSpec;
    /// `CCRCFAIL`, bit 0.
    pub const CCRCFAIL: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `DCRCFAIL`, bit 1.
    pub const DCRCFAIL: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `CTIMEOUT`, bit 2.
    pub const CTIMEOUT: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `DTIMEOUT`, bit 3.
    pub const DTIMEOUT: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `TXUNDERR`, bit 4.
    pub const TXUNDERR: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `RXOVERR`, bit 5.
    pub const RXOVERR: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `CMDREND`, bit 6.
    pub const CMDREND: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `CMDSENT`, bit 7.
    pub const CMDSENT: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `DATAEND`, bit 8.
    pub const DATAEND: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `STBITERR`, bit 9.
    pub const STBITERR: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `DBCKEND`, bit 10.
    pub const DBCKEND: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `CMDACT`, bit 11.
    pub const CMDACT: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `TXACT`, bit 12.
    pub const TXACT: &FieldSpec = &super::REGISTERS[13].fields[12];
    /// `RXACT`, bit 13.
    pub const RXACT: &FieldSpec = &super::REGISTERS[13].fields[13];
    /// `TXFIFOHE`, bit 14.
    pub const TXFIFOHE: &FieldSpec = &super::REGISTERS[13].fields[14];
    /// `RXFIFOHF`, bit 15.
    pub const RXFIFOHF: &FieldSpec = &super::REGISTERS[13].fields[15];
    /// `TXFIFOF`, bit 16.
    pub const TXFIFOF: &FieldSpec = &super::REGISTERS[13].fields[16];
    /// `RXFIFOF`, bit 17.
    pub const RXFIFOF: &FieldSpec = &super::REGISTERS[13].fields[17];
    /// `TXFIFOE`, bit 18.
    pub const TXFIFOE: &FieldSpec = &super::REGISTERS[13].fields[18];
    /// `RXFIFOE`, bit 19.
    pub const RXFIFOE: &FieldSpec = &super::REGISTERS[13].fields[19];
    /// `TXDAVL`, bit 20.
    pub const TXDAVL: &FieldSpec = &super::REGISTERS[13].fields[20];
    /// `RXDAVL`, bit 21.
    pub const RXDAVL: &FieldSpec = &super::REGISTERS[13].fields[21];
    /// `SDIOIT`, bit 22.
    pub const SDIOIT: &FieldSpec = &super::REGISTERS[13].fields[22];
    /// `CEATAEND`, bit 23.
    pub const CEATAEND: &FieldSpec = &super::REGISTERS[13].fields[23];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `CCRCFAILC`, bit 0.
    pub const CCRCFAILC: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `DCRCFAILC`, bit 1.
    pub const DCRCFAILC: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `CTIMEOUTC`, bit 2.
    pub const CTIMEOUTC: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `DTIMEOUTC`, bit 3.
    pub const DTIMEOUTC: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `TXUNDERRC`, bit 4.
    pub const TXUNDERRC: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `RXOVERRC`, bit 5.
    pub const RXOVERRC: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `CMDRENDC`, bit 6.
    pub const CMDRENDC: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `CMDSENTC`, bit 7.
    pub const CMDSENTC: &FieldSpec = &super::REGISTERS[14].fields[7];
    /// `DATAENDC`, bit 8.
    pub const DATAENDC: &FieldSpec = &super::REGISTERS[14].fields[8];
    /// `STBITERRC`, bit 9.
    pub const STBITERRC: &FieldSpec = &super::REGISTERS[14].fields[9];
    /// `DBCKENDC`, bit 10.
    pub const DBCKENDC: &FieldSpec = &super::REGISTERS[14].fields[10];
    /// `SDIOITC`, bit 22.
    pub const SDIOITC: &FieldSpec = &super::REGISTERS[14].fields[11];
    /// `CEATAENDC`, bit 23.
    pub const CEATAENDC: &FieldSpec = &super::REGISTERS[14].fields[12];
}

/// The fields of `MASK`.
pub mod mask {
    use super::FieldSpec;
    /// `CCRCFAILIE`, bit 0.
    pub const CCRCFAILIE: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `DCRCFAILIE`, bit 1.
    pub const DCRCFAILIE: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `CTIMEOUTIE`, bit 2.
    pub const CTIMEOUTIE: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `DTIMEOUTIE`, bit 3.
    pub const DTIMEOUTIE: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `TXUNDERRIE`, bit 4.
    pub const TXUNDERRIE: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `RXOVERRIE`, bit 5.
    pub const RXOVERRIE: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `CMDRENDIE`, bit 6.
    pub const CMDRENDIE: &FieldSpec = &super::REGISTERS[15].fields[6];
    /// `CMDSENTIE`, bit 7.
    pub const CMDSENTIE: &FieldSpec = &super::REGISTERS[15].fields[7];
    /// `DATAENDIE`, bit 8.
    pub const DATAENDIE: &FieldSpec = &super::REGISTERS[15].fields[8];
    /// `STBITERRIE`, bit 9.
    pub const STBITERRIE: &FieldSpec = &super::REGISTERS[15].fields[9];
    /// `DBCKENDIE`, bit 10.
    pub const DBCKENDIE: &FieldSpec = &super::REGISTERS[15].fields[10];
    /// `CMDACTIE`, bit 11.
    pub const CMDACTIE: &FieldSpec = &super::REGISTERS[15].fields[11];
    /// `TXACTIE`, bit 12.
    pub const TXACTIE: &FieldSpec = &super::REGISTERS[15].fields[12];
    /// `RXACTIE`, bit 13.
    pub const RXACTIE: &FieldSpec = &super::REGISTERS[15].fields[13];
    /// `TXFIFOHEIE`, bit 14.
    pub const TXFIFOHEIE: &FieldSpec = &super::REGISTERS[15].fields[14];
    /// `RXFIFOHFIE`, bit 15.
    pub const RXFIFOHFIE: &FieldSpec = &super::REGISTERS[15].fields[15];
    /// `TXFIFOFIE`, bit 16.
    pub const TXFIFOFIE: &FieldSpec = &super::REGISTERS[15].fields[16];
    /// `RXFIFOFIE`, bit 17.
    pub const RXFIFOFIE: &FieldSpec = &super::REGISTERS[15].fields[17];
    /// `TXFIFOEIE`, bit 18.
    pub const TXFIFOEIE: &FieldSpec = &super::REGISTERS[15].fields[18];
    /// `RXFIFOEIE`, bit 19.
    pub const RXFIFOEIE: &FieldSpec = &super::REGISTERS[15].fields[19];
    /// `TXDAVLIE`, bit 20.
    pub const TXDAVLIE: &FieldSpec = &super::REGISTERS[15].fields[20];
    /// `RXDAVLIE`, bit 21.
    pub const RXDAVLIE: &FieldSpec = &super::REGISTERS[15].fields[21];
    /// `SDIOITIE`, bit 22.
    pub const SDIOITIE: &FieldSpec = &super::REGISTERS[15].fields[22];
    /// `CEATAENDIE`, bit 23.
    pub const CEATAENDIE: &FieldSpec = &super::REGISTERS[15].fields[23];
}

/// The fields of `FIFOCNT`.
pub mod fifocnt {
    use super::FieldSpec;
    /// `FIFOCOUNT`, bits 0..=23.
    pub const FIFOCOUNT: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `FIFO`.
pub mod fifo {
    use super::FieldSpec;
    /// `FIFOData`, bits 0..=31.
    pub const FIFODATA: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 18] = [
    RegisterSpec { name: "POWER", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWRCTRL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CLKCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLKDIV", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLKEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRSAV", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BYPASS", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WIDBUS", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NEGEDGE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HWFC_EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARG", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMDARG", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CMD", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMDINDEX", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITRESP", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITINT", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPEND", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSMEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOSuspend", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENCMDcompl", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "nIEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CE_ATACMD", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESPCMD", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RESPCMD", bit: 0, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS1", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP2", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP3", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS3", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RESP4", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CARDSTATUS4", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DTIMER", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATATIME", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DLEN", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATALENGTH", bit: 0, width: 25, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCTRL", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTDIR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTMODE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBLOCKSIZE", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWSTART", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWSTOP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCOUNT", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATACOUNT", bit: 0, width: 25, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "STA", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAIL", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAIL", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUT", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUT", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERR", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERR", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDREND", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENT", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAEND", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STBITERR", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKEND", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDACT", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXACT", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXACT", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOHE", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOHF", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOF", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOE", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOE", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDAVL", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXDAVL", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOIT", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEATAEND", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAILC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAILC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUTC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUTC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERRC", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERRC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDRENDC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENTC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAENDC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STBITERRC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKENDC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOITC", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEATAENDC", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MASK", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCRCFAILIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRCFAILIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTIMEOUTIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTIMEOUTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUNDERRIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVERRIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDRENDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDSENTIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAENDIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STBITERRIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBCKENDIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMDACTIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXACTIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXACTIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOHEIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOHFIE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOFIE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOFIE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFIFOEIE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFIFOEIE", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDAVLIE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXDAVLIE", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOITIE", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEATAENDIE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FIFOCNT", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FIFOCOUNT", bit: 0, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FIFO", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FIFOData", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];