rigless 0.0.2

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; needs the rigless-sidecar package from rigless-labs/qemu
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `SPI1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `SR` at offset `0x8`, resets to `0x0000_0002`, read-write.
    Sr = 2,
    /// `DR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dr = 3,
    /// `CRCPR` at offset `0x10`, resets to `0x0000_0007`, read-write.
    Crcpr = 4,
    /// `RXCRCR` at offset `0x14`, resets to `0x0000_0000`, read-only.
    Rxcrcr = 5,
    /// `TXCRCR` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Txcrcr = 6,
    /// `I2SCFGR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    I2scfgr = 7,
    /// `I2SPR` at offset `0x20`, resets to `0x0000_000A`, read-write.
    I2spr = 8,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 9] = [Self::Cr1, Self::Cr2, Self::Sr, Self::Dr, Self::Crcpr, Self::Rxcrcr, Self::Txcrcr, Self::I2scfgr, Self::I2spr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `CPHA`, bit 0.
    pub const CPHA: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `CPOL`, bit 1.
    pub const CPOL: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `MSTR`, bit 2.
    pub const MSTR: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `BR`, bits 3..=5.
    pub const BR: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `SPE`, bit 6.
    pub const SPE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `LSBFIRST`, bit 7.
    pub const LSBFIRST: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `SSI`, bit 8.
    pub const SSI: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `SSM`, bit 9.
    pub const SSM: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `RXONLY`, bit 10.
    pub const RXONLY: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `DFF`, bit 11.
    pub const DFF: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `CRCNEXT`, bit 12.
    pub const CRCNEXT: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `CRCEN`, bit 13.
    pub const CRCEN: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `BIDIOE`, bit 14.
    pub const BIDIOE: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `BIDIMODE`, bit 15.
    pub const BIDIMODE: &FieldSpec = &super::REGISTERS[0].fields[13];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `RXDMAEN`, bit 0.
    pub const RXDMAEN: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TXDMAEN`, bit 1.
    pub const TXDMAEN: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SSOE`, bit 2.
    pub const SSOE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `FRF`, bit 4.
    pub const FRF: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `ERRIE`, bit 5.
    pub const ERRIE: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `RXNEIE`, bit 6.
    pub const RXNEIE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `TXEIE`, bit 7.
    pub const TXEIE: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `RXNE`, bit 0, read-only.
    pub const RXNE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TXE`, bit 1, read-only.
    pub const TXE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `CHSIDE`, bit 2, read-only.
    pub const CHSIDE: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `UDR`, bit 3, read-only.
    pub const UDR: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `CRCERR`, bit 4.
    pub const CRCERR: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `MODF`, bit 5, read-only.
    pub const MODF: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `OVR`, bit 6, read-only.
    pub const OVR: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `BSY`, bit 7, read-only.
    pub const BSY: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `TIFRFE`, bit 8, read-only.
    pub const TIFRFE: &FieldSpec = &super::REGISTERS[2].fields[8];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DR`, bits 0..=15.
    pub const DR: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `CRCPR`.
pub mod crcpr {
    use super::FieldSpec;
    /// `CRCPOLY`, bits 0..=15.
    pub const CRCPOLY: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `RXCRCR`.
pub mod rxcrcr {
    use super::FieldSpec;
    /// `RxCRC`, bits 0..=15.
    pub const RXCRC: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `TXCRCR`.
pub mod txcrcr {
    use super::FieldSpec;
    /// `TxCRC`, bits 0..=15.
    pub const TXCRC: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `I2SCFGR`.
pub mod i2scfgr {
    use super::FieldSpec;
    /// `CHLEN`, bit 0.
    pub const CHLEN: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `DATLEN`, bits 1..=2.
    pub const DATLEN: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `CKPOL`, bit 3.
    pub const CKPOL: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `I2SSTD`, bits 4..=5.
    pub const I2SSTD: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `PCMSYNC`, bit 7.
    pub const PCMSYNC: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `I2SCFG`, bits 8..=9.
    pub const I2SCFG: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `I2SE`, bit 10.
    pub const I2SE: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `I2SMOD`, bit 11.
    pub const I2SMOD: &FieldSpec = &super::REGISTERS[7].fields[7];
}

/// The fields of `I2SPR`.
pub mod i2spr {
    use super::FieldSpec;
    /// `I2SDIV`, bits 0..=7.
    pub const I2SDIV: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `ODD`, bit 8.
    pub const ODD: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `MCKOE`, bit 9.
    pub const MCKOE: &FieldSpec = &super::REGISTERS[8].fields[2];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 9] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CPHA", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPOL", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTR", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFIRST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSI", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSM", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXONLY", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFF", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCNEXT", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BIDIOE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BIDIMODE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXDMAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXDMAEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSOE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FRF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNEIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x8, width: Width::W32, reset: 0x0000_0002, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXNE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHSIDE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDR", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCERR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BSY", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIFRFE", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DR", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CRCPR", offset: 0x10, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CRCPOLY", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RXCRCR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RxCRC", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TXCRCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TxCRC", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "I2SCFGR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CHLEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLEN", bit: 1, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKPOL", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SSTD", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCMSYNC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SCFG", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SMOD", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "I2SPR", offset: 0x20, width: Width::W32, reset: 0x0000_000A, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "I2SDIV", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODD", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCKOE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];