open-vaf 0.4.2

A compiler frontend for VerilogA aimed predominently at compact modelling
Documentation 
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module test begin
    analog begin
        if (V(x) > 32)
            I(x)<+(V(x)-V0)^2/(R1R2);
        else if (V(x) > 10 begin
            z = y==0?40:32*y)
            I(x)<+(V(x)-V0)^2/(z);
        end else
            I(x) <+ V(x)*z;
    end
endmodule