open-vaf 0.4.2

A compiler frontend for VerilogA aimed predominently at compact modelling
Documentation
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/*
 * ******************************************************************************************
 * Copyright (c) 2019 Pascal Kuthe. This file is part of the OpenVAF project.
 * It is subject to the license terms in the LICENSE file found in the top-level directory
 *  of this distribution and at  https://gitlab.com/DSPOM/OpenVAF/blob/master/LICENSE.
 *  No part of OpenVAF, including this file, may be copied, modified, propagated, or
 *  distributed except according to the terms contained in the LICENSE file.
 * *****************************************************************************************
 */
module test (output a,input b);
    branch (a,b) ab1,ab2;
    branch (<a>) pa;
    branch (<b>) pb;
endmodule