#[doc = "Register `MRCC_CLKOUT_CLKDIV` reader"]
pub type R = crate::R<MrccClkoutClkdivSpec>;
#[doc = "Register `MRCC_CLKOUT_CLKDIV` writer"]
pub type W = crate::W<MrccClkoutClkdivSpec>;
#[doc = "Field `DIV` reader - Functional Clock Divider"]
pub type DivR = crate::FieldReader;
#[doc = "Field `DIV` writer - Functional Clock Divider"]
pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Reset divider counter\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Reset {
#[doc = "0: Reset is released/disabled (clock is running)"]
Deasserted = 0,
#[doc = "1: Reset is active/enabled (clock is NOT running)"]
Asserted = 1,
}
impl From<Reset> for bool {
#[inline(always)]
fn from(variant: Reset) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RESET` writer - Reset divider counter"]
pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
impl<'a, REG> ResetW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Reset is released/disabled (clock is running)"]
#[inline(always)]
pub fn deasserted(self) -> &'a mut crate::W<REG> {
self.variant(Reset::Deasserted)
}
#[doc = "Reset is active/enabled (clock is NOT running)"]
#[inline(always)]
pub fn asserted(self) -> &'a mut crate::W<REG> {
self.variant(Reset::Asserted)
}
}
#[doc = "Halt divider counter\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Halt {
#[doc = "0: Halt is inactive/disabled (clock is running)"]
Deasserted = 0,
#[doc = "1: Halt is active/enabled (clock is NOT running)"]
Asserted = 1,
}
impl From<Halt> for bool {
#[inline(always)]
fn from(variant: Halt) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HALT` reader - Halt divider counter"]
pub type HaltR = crate::BitReader<Halt>;
impl HaltR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Halt {
match self.bits {
false => Halt::Deasserted,
true => Halt::Asserted,
}
}
#[doc = "Halt is inactive/disabled (clock is running)"]
#[inline(always)]
pub fn is_deasserted(&self) -> bool {
*self == Halt::Deasserted
}
#[doc = "Halt is active/enabled (clock is NOT running)"]
#[inline(always)]
pub fn is_asserted(&self) -> bool {
*self == Halt::Asserted
}
}
#[doc = "Field `HALT` writer - Halt divider counter"]
pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>;
impl<'a, REG> HaltW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Halt is inactive/disabled (clock is running)"]
#[inline(always)]
pub fn deasserted(self) -> &'a mut crate::W<REG> {
self.variant(Halt::Deasserted)
}
#[doc = "Halt is active/enabled (clock is NOT running)"]
#[inline(always)]
pub fn asserted(self) -> &'a mut crate::W<REG> {
self.variant(Halt::Asserted)
}
}
#[doc = "Divider status flag\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Unstab {
#[doc = "0: Clock divider is stable"]
Stable = 0,
#[doc = "1: Clock divider is unstable"]
Unstable = 1,
}
impl From<Unstab> for bool {
#[inline(always)]
fn from(variant: Unstab) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `UNSTAB` reader - Divider status flag"]
pub type UnstabR = crate::BitReader<Unstab>;
impl UnstabR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Unstab {
match self.bits {
false => Unstab::Stable,
true => Unstab::Unstable,
}
}
#[doc = "Clock divider is stable"]
#[inline(always)]
pub fn is_stable(&self) -> bool {
*self == Unstab::Stable
}
#[doc = "Clock divider is unstable"]
#[inline(always)]
pub fn is_unstable(&self) -> bool {
*self == Unstab::Unstable
}
}
impl R {
#[doc = "Bits 0:3 - Functional Clock Divider"]
#[inline(always)]
pub fn div(&self) -> DivR {
DivR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 30 - Halt divider counter"]
#[inline(always)]
pub fn halt(&self) -> HaltR {
HaltR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Divider status flag"]
#[inline(always)]
pub fn unstab(&self) -> UnstabR {
UnstabR::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MRCC_CLKOUT_CLKDIV")
.field("div", &self.div())
.field("halt", &self.halt())
.field("unstab", &self.unstab())
.finish()
}
}
impl W {
#[doc = "Bits 0:3 - Functional Clock Divider"]
#[inline(always)]
pub fn div(&mut self) -> DivW<'_, MrccClkoutClkdivSpec> {
DivW::new(self, 0)
}
#[doc = "Bit 29 - Reset divider counter"]
#[inline(always)]
pub fn reset(&mut self) -> ResetW<'_, MrccClkoutClkdivSpec> {
ResetW::new(self, 29)
}
#[doc = "Bit 30 - Halt divider counter"]
#[inline(always)]
pub fn halt(&mut self) -> HaltW<'_, MrccClkoutClkdivSpec> {
HaltW::new(self, 30)
}
}
#[doc = "CLKOUT clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_clkout_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_clkout_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MrccClkoutClkdivSpec;
impl crate::RegisterSpec for MrccClkoutClkdivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mrcc_clkout_clkdiv::R`](R) reader structure"]
impl crate::Readable for MrccClkoutClkdivSpec {}
#[doc = "`write(|w| ..)` method takes [`mrcc_clkout_clkdiv::W`](W) writer structure"]
impl crate::Writable for MrccClkoutClkdivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MRCC_CLKOUT_CLKDIV to value 0x4000_0000"]
impl crate::Resettable for MrccClkoutClkdivSpec {
const RESET_VALUE: u32 = 0x4000_0000;
}