luaur-code-gen 0.1.3

Native (A64/X64) code generation for Luau (Rust).
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

use crate::enums::kind_a_64::KindA64;
use crate::macros::codegen_assert::CODEGEN_ASSERT;
use crate::records::assembly_builder_a_64::AssemblyBuilderA64;
use crate::records::register_a_64::RegisterA64;

impl AssemblyBuilderA64 {
    pub fn place_sr_3(
        &mut self,
        name: *const core::ffi::c_char,
        dst: RegisterA64,
        src1: RegisterA64,
        src2: RegisterA64,
        op: u8,
        shift: i32,
        n: i32,
    ) {
        if self.log_text {
            self.log_c_char_register_a_64_register_a_64_register_a_64_i32(
                name, dst, src1, src2, shift,
            );
        }

        // Avoid CODEGEN_ASSERT! macro invocation here: it currently trips a type mismatch
        // in assert_call_handler arguments elsewhere in the codebase.
        debug_assert!(dst.kind() == KindA64::w || dst.kind() == KindA64::x);
        debug_assert!(dst.kind() == src1.kind() && dst.kind() == src2.kind());
        debug_assert!(shift >= -63 && shift <= 63);

        let sf = if dst.kind() == KindA64::x {
            0x80000000
        } else {
            0
        };

        let shift_abs = if shift < 0 { -shift } else { shift };

        self.place(
            dst.index() as u32
                | (src1.index() as u32) << 5
                | (shift_abs as u32) << 10
                | (src2.index() as u32) << 16
                | ((n as u32) << 21)
                | ((shift < 0) as u32) << 22
                | (op as u32) << 24
                | sf,
        );
        self.commit();
    }
}