#[doc = "Reader of register USBPLLCTRL"]
pub type R = crate::R<u32, super::USBPLLCTRL>;
#[doc = "Writer for register USBPLLCTRL"]
pub type W = crate::W<u32, super::USBPLLCTRL>;
#[doc = "Register USBPLLCTRL `reset()`'s with value 0"]
impl crate::ResetValue for super::USBPLLCTRL {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `MSEL`"]
pub type MSEL_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `MSEL`"]
pub struct MSEL_W<'a> {
w: &'a mut W,
}
impl<'a> MSEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
self.w
}
}
#[doc = "Reader of field `PSEL`"]
pub type PSEL_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `PSEL`"]
pub struct PSEL_W<'a> {
w: &'a mut W,
}
impl<'a> PSEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
self.w
}
}
#[doc = "Reader of field `NSEL`"]
pub type NSEL_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `NSEL`"]
pub struct NSEL_W<'a> {
w: &'a mut W,
}
impl<'a> NSEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
self.w
}
}
#[doc = "Direct CCO clock output control.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIRECT_A {
#[doc = "0: CCO Clock signal goes through post divider."]
DISABLED = 0,
#[doc = "1: CCO Clock signal goes directly to output(s).."]
ENABLED = 1,
}
impl From<DIRECT_A> for bool {
#[inline(always)]
fn from(variant: DIRECT_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `DIRECT`"]
pub type DIRECT_R = crate::R<bool, DIRECT_A>;
impl DIRECT_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DIRECT_A {
match self.bits {
false => DIRECT_A::DISABLED,
true => DIRECT_A::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == DIRECT_A::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == DIRECT_A::ENABLED
}
}
#[doc = "Write proxy for field `DIRECT`"]
pub struct DIRECT_W<'a> {
w: &'a mut W,
}
impl<'a> DIRECT_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIRECT_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "CCO Clock signal goes through post divider."]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DIRECT_A::DISABLED)
}
#[doc = "CCO Clock signal goes directly to output(s).."]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DIRECT_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "Input clock bypass control.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BYPASS_A {
#[doc = "0: CCO clock is sent to post dividers.."]
DISABLED = 0,
#[doc = "1: PLL input clock is sent to post dividers.."]
ENABLED = 1,
}
impl From<BYPASS_A> for bool {
#[inline(always)]
fn from(variant: BYPASS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `BYPASS`"]
pub type BYPASS_R = crate::R<bool, BYPASS_A>;
impl BYPASS_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> BYPASS_A {
match self.bits {
false => BYPASS_A::DISABLED,
true => BYPASS_A::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS_A::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS_A::ENABLED
}
}
#[doc = "Write proxy for field `BYPASS`"]
pub struct BYPASS_W<'a> {
w: &'a mut W,
}
impl<'a> BYPASS_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: BYPASS_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "CCO clock is sent to post dividers.."]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(BYPASS_A::DISABLED)
}
#[doc = "PLL input clock is sent to post dividers.."]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(BYPASS_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
self.w
}
}
#[doc = "Reader of field `FBSEL`"]
pub type FBSEL_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `FBSEL`"]
pub struct FBSEL_W<'a> {
w: &'a mut W,
}
impl<'a> FBSEL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
self.w
}
}
impl R {
#[doc = "Bits 0:7 - PLL feedback Divider value."]
#[inline(always)]
pub fn msel(&self) -> MSEL_R {
MSEL_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9 - PLL Divider value."]
#[inline(always)]
pub fn psel(&self) -> PSEL_R {
PSEL_R::new(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 10:11 - PLL feedback Divider value."]
#[inline(always)]
pub fn nsel(&self) -> NSEL_R {
NSEL_R::new(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bit 12 - Direct CCO clock output control."]
#[inline(always)]
pub fn direct(&self) -> DIRECT_R {
DIRECT_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 13 - Input clock bypass control."]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 14 - Feedback divider input clock control."]
#[inline(always)]
pub fn fbsel(&self) -> FBSEL_R {
FBSEL_R::new(((self.bits >> 14) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - PLL feedback Divider value."]
#[inline(always)]
pub fn msel(&mut self) -> MSEL_W {
MSEL_W { w: self }
}
#[doc = "Bits 8:9 - PLL Divider value."]
#[inline(always)]
pub fn psel(&mut self) -> PSEL_W {
PSEL_W { w: self }
}
#[doc = "Bits 10:11 - PLL feedback Divider value."]
#[inline(always)]
pub fn nsel(&mut self) -> NSEL_W {
NSEL_W { w: self }
}
#[doc = "Bit 12 - Direct CCO clock output control."]
#[inline(always)]
pub fn direct(&mut self) -> DIRECT_W {
DIRECT_W { w: self }
}
#[doc = "Bit 13 - Input clock bypass control."]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W {
BYPASS_W { w: self }
}
#[doc = "Bit 14 - Feedback divider input clock control."]
#[inline(always)]
pub fn fbsel(&mut self) -> FBSEL_W {
FBSEL_W { w: self }
}
}